AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 14

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

COL
Collision
Input, Active LOW
When this pin is asserted by an external arbiter, it sig-
nifies that more than one IMR2 device is active and that
each IMR2 device should generate the Collision Jam
Sequence independently.
ECLK
Bus Clock
Input/Output
Data transitions on the expansion bus on DAT are syn-
chronized to this clock. ECLK is a 10-MHz output clock
when DAT is transmitting and a 10-MHz input clock
when DAT is receiving. ECLK is only used when the ex-
pansion bus is operated in the asynchronous mode.
ECLK should be terminated to ground with a 1 k resis-
tor. ECLK should be ignored in the synchronous mode.
MACEN
MAC Enable
Input, Active LOW
When this pin is asserted, data on the expansion bus is
included in MIB statistics. This is typically used when a
MAC is driving the expansion bus.
MATCHO
This pin should be tied to +5 V through a 1 k
MATCHI
This pin should be tied to +5 V through a 1 k
FRAME
Packet Framing Signal
Input/Output, Active LOW
FRAME defines the beginning and end of a packet.
FRAME indicates valid data on the DAT pin when the ex-
pansion bus is in the asynchronous mode. FRAME is an
output on the IMR2 device when it is transmitting over the
expansion bus. It is an input on all other IMR2 devices.
XMODE
Expansion Bus Mode
Input
XMODE determines the mode of the expansion bus.
XMODE should not be changed after RST. Although
changing XMODE after RST will change the expansion
bus mode, the operation is unpredictable. Therefore, it
is recommended that XMODE be tied either HIGH or
LOW, depending on the desired expansion bus mode.
14
10% resistor.
10% resistor.
XMODE
1
0
Asynchronous
Synchronous (IMR/IMR+)
Mode
P R E L I M I N A R Y
Am79C983A
XENA
Port Enable
Input
XENA sets the default mode of the ports. It is used
when RST transitions from LOW to HIGH.
Note: XENA only controls the default state. Once
reset is completed, the enabling and disabling of ports
is under software control. It is recommended that
XENA be tied either HIGH or LOW, depending on the
desired default state.
Packet Report Port
PDAT
Packet Report
Output, High Impedance
PDAT outputs the beginning portion of a packet fol-
lowed by packet status information. The size of the be-
ginning portion is user programmable. If a second
packet arrives before PDAT finishes transmitting status
information, the second packet and corresponding sta-
tus information are not transmitted over PDAT. The
packet is aborted on collision.
PENAI
Packet Report Enable Input
Input, Active LOW
PENAI senses when another device is transmitting
over PDAT.
PENAO
Packet Report Enable Output
Output, Active LOW, Open Drain
PENAO is TRUE when the IMR2 device is transmitting
data over PDAT. If a second packet arrives before PDAT
is finished transmitting status information, PENAO re-
mains active for the second packet.
PDRV
Packet Drive
Output, Active LOW
PDRV is TRUE when the IMR2 device is transmitting
data over PDAT. If a second packet arrives before PDAT
is finished transmitting status, PDRV goes FALSE after
the status is transmitted.
PCLK
Packet Report Clock
Output, High Impedance
PCLK is a 10-MHz clock. PDAT transitions are synchro-
nized to PCLK.
XENA
1
0
All ports are enabled.
All ports are disabled. The output drivers
are in a high impedance state.
Default