AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 52

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

Notes:
1. Parameter is not tested.
2. ECLK is dependent on the frequency of the data on the active port.
3. (R)DI pulses narrower than tPWODI (min) will be rejected; (R)DI pulses wider than tPWODI (max) will turn internal (R)DI car-
4. (R)DI pulses narrower than tPWKDI (min) will maintain internal (R)DI carrier sense on; (R)DI pulses wider than tPWKDI(max)
5. (R)CI pulses narrower than tPWOCI (min) will be rejected; (R)CI pulses wider than tPWOCI (max) will turn internal (R)CI car-
6. (R)CI pulses narrower than tPWKCI (min) will maintain internal (R)CI carrier sense; (R)CI pulses longer than tPWKCI (max)
7. PDI pulses narrower than tPWOPDI (min) will be rejected; PDI pulses wider than tPWOPDI (max) will turn internal PDI carrier
52
Parameter
Microprocessor Interface Timing
Management Port Timing
Packet Report Port Timing
t
t
Symbol
MDHOLD
t
t
t
EDHOLD
t
t
t
t
t
MSSHD
t
MDSET
MAHLD
t
t
MSSSU
rier sense on.
will turn internal (R)DI carrier sense off.
rier sense on.
will turn internal (R)CI carrier sense off.
MASET
EDSET
t
t
sense on.
t
t
MHDR
MSDO
MHDZ
t
MSSO
t
t
t
t
RDYD
RDYH
DOUT
ELDR
REST
t
DOH
t
t
CDS
CDH
CSH
CSS
PRV
DIS
DIH
MCLK HIGH to DAT/JAM Driven
MCLK HIGH TO DAT/JAM Not Driven
DAT/JAM Setup Time to MCLK
DAT/JAM Hold Time from MCLK
COL/ACK Setup Time to MCLK
COL/ACK Hold Time to MCLK
ECLK LOW to DAT Switching
DAT Setup to ECLK
DAT Hold Time from ECLK
C/D Setup Time with Respect to RD/WR
Leading Edge
C/D Hold Time with Respect to RD/WR Rising
Edge
CS Setup Time with Respect to RD/WR Fall-
ing Edge
CS Hold Time with Respect to RD/WR Rising
RDY Leading Edge Delay
RDY HIGH to RD/WR Rising
Data Out to RDY HIGH
Data Out HOLD after RD HIGH
Data In Setup Time with Respect to WR Ris-
ing Edge
Rest Period between MPI Operations (Time
between the Earliest CS/RD/WR Going HIGH
to the Next CS/RD/WR Going LOW, whichev-
er is the Latest
Data In HOLD after WR HIGH
MCLK to SDATA
MCLK to DIR[1:0]
SDATA Setup Time
SDATA Hold Time
PCLK LOW to PDAT Switching
Parameter Description
P R E L I M I N A R Y
Am79C983A
Test Conditions
C
C
C
C
C
C
L
L
L
L
L
L
=100pF
=100pF
=100pF
=100pF
=100pF
=100pF
Min
150
10
10
10
14
10
14
10
10
50
10
25
10
10
10
10
14
5
0
0
0
0
-
-
-
Max
40
40
20
25
50
40
40
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns