AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 28

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

CRS and COLX are the only valid attributes for the Ex-
pansion Bus. Therefore, when BSEL is HIGH, LD[6]
has the Expansion Bus attribute for CRS and COLX.
Using AUI/RAUI for 10BASE-T Ports
The IMR2 device obtains Link and Polarity status from
the serial data interface (SDATA [3:0]). When a single
IMR2 device uses four QuIET devices, two of the ports
on the fourth QuIET device connect to the AUI and
RAUI ports of the IMR2. The two remaining ports on the
fourth QuIET device connect to a second IMR2 device.
Only the IMR2 device driving the serial interface to this
QuIET device has Link and Polarity Status. Therefore,
when BSEL is HIGH and either LINK or PART are
HIGH, LD[7:6] contains Link Status or Polarity Status,
respectively, of ports 2 and 3 of the fourth QuIET de-
vice.
If the AUI and RAUI ports are connected to a MAU
(other than a QuIET device), LINK actually reports
Loopback Error, where 1 indicates no loopback error
and 0 indicates a Loopback Error. The state of POL will
reflect the received polarity value on SDATA. The rec-
ommended implementation is shown in 6. The attribute
select pins are connected to open-collector or open-
drain inverters. The buffers connected to LD[7:0] have
high-impedance outputs. They must source enough
current to turn on the LEDs (typically 20 mA). CMOS
devices that have a rail-to-rail output are recom-
mended. Also, multiple open-collector inverters can be
used in conjunction with multiple drives to overcome
maximum current source/drain issues.
CRS and COLX signals are stretched to enhance vi-
sual recognition, i.e., they will remain active for some
time even if the corresponding condition has expired.
Once carrier sense is active, CRS will remain active for
a minimum of 4 ms. Once a collision is detected, COLX
will remain active for at least 4 ms.
28
LD[7:0]
COLX
BSEL
PART
CRS
LINK
POL
Figure 5. Visual Monitor Signals
P R E L I M I N A R Y
19879B-9
Am79C983A
Intrusion Protection
The IMR2 device provides protection against intrusion,
which is defined here as the unauthorized transmitting
of packets onto the network.
Each port has two address registers associated with it:
Last Source Address Register and Preferred Source
Address Register. Unless it is locked, the Last Source
Address Register contains the source address of the
previous packet received by that port. The Preferred
Source Address Register contains the source address
that the system considers valid for that port. Both reg-
isters may be written.
If the valid address is known by the system, it may be
written into both registers. If it is not known by the sys-
tem, the Last Source Address Register is monitored by
the system. After a packet is received by the port, the
source address may be written into the Preferred
Source Address Register by the system.
The Last Source Address Register may be locked. If
the Last Source Address Register is locked, a mis-
match between the packet's source address and the
Last Source Address Register will not result in a
change in the Last Source Address Register. The only
way the register can be changed is by accessing it
through the node processor interface. The control reg-
ister for this is the Last Source Address Lock Register.
The IMR2 device provides two applicable interrupts:
Source Address Changed Interrupt and Intruder Inter-
rupt. Both interrupts can be masked on a port-by-port
basis. Source Address Changed Interrupt compares
the incoming packet's source address against two
registers: Last Source Address Register and the Pre-
ferred Source Address Register. The interrupt is set
when the source address of the incoming packet does
not match both registers. Intruder Interrupt compares
Figure 6. Visual Monitoring Application -
BSEL
POL
LD [7:0]
PART
LINK
CRS
COLX
Simplified Schematic
EN
EN
19879B-10