AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 30

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

Byte 0
Byte 1
Unless otherwise indicated, the discussion of registers
that are concerned with status or control on the IMR2
device will have the following format.
IMR2 Device Registers
Where
Unless otherwise indicated, the discussion of regis-
ters that are concerned with status or control on
QuIET devices connected to the IMR2 device will
have the following format.
QuIET Device Registers
Where:
Note: The port on the QuIET device may be connected
to a port on another IMR2 device.
Status Register
The Status Register can be accessed at any time by
reading the Command Register.
The 8-bit quantity read has the following format:
I
E
S
30
Byte 0
Byte 1
C Port Read
I
Interrupt. This bit reflects the state of the INT output
pin. If this bit is set to 1, then this IMR2 device is
driving the INT pin. Note that INT is an open drain
output and that multiple devices may share the
same interrupt signal.
Transceiver Interface Changed. This bit is set if the
interface to at least one SDATA input has changed
from a QuIET device to a non-QuIET device or
from a non-QuIET device to a QuIET device.
Source Address Match. This bit is set if the inter-
rupt is caused by a source address match of the
P n refers to a PAUI port.
AUI refers to the AUI port
RAUI refers to the RAUI port
EP refers to the Expansion Bus
TPn refers to a TP port on a QuIET device.
SPn refers to a QuIET device port connected to
the AUI port or PAUI port on this device or to any
port on another IMR2 device.
:
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
D Port Read/Write
E
D Port Read/Write
P7
0
P6
EP/0
S
P5
RAUI
X
P4
AUI P11 P10 P9
B
TP11 TP
P3
M
P2
10
P
TP9 TP8
P R E L I M I N A R Y
P1
L
P0
P8
Am79C983A
B
M
P
L
X
Register Bank 0: Repeater Registers
These registers are accessed by writing the bit pattern
0000 0000 to the C Register. The contents of all at-
tribute counters are indeterminate upon power up.
Source Address Match Register
Address:
This is a read/write register. The six bytes are read or
written in LOW byte to HIGH byte order. The sequence
is (re)started once the C register is programmed for ac-
cess to this register. This register may be used to track
nodes within a LAN by reporting the port that received
a packet with a specific source address. The source ad-
dress field of incoming packets is always compared
with the 48-bit quantity stored in this register. The initial
value of this register is indeterminate.
The IMR2 indicates a match by setting the correspond-
ing bit in the Source Address Match Interrupt Register
of the receiving port. If the Source Address Match In-
terrupt Enable bit is enabled, then the INT output pin is
driven LOW. The set bit(s) in the Source Address
Match Interrupt Registers are cleared when these reg-
isters are read.
Note: Once the sequence is started, all six bytes have
to be written or the contents do not change.
Byte 0
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
incoming data packet. This bit remains set until the
Source Address Match Status Register is read.
Bit Rate Error and Partition. This bit is set if the
interrupt is caused by either a bit rate error or a
change in the partition status of a port.
Source Address Change. This bit is set if the inter-
rupt is caused by a change in the source address
or a mismatch between the incoming source ad-
dress and a preferred address.
Polarity and SQE. This bit is set if the interrupt is
caused by a change in the SQE test results or a
polarity change.
Link and Loopback. This bit is set if the interrupt is
caused by a link or loopback change.
Reserved. The
are indeterminate.
D Port Read/Write
bit 7
bit 47
MSB
1110 1010
values
of
reserved
bit 0
bit 40
LSB
bits