AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 15

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

PTAG
Packet Tag
Output, HIGH Impedance, Active LOW
PTAG indicates when the status frame is being trans-
mitted over PDAT. It is asserted when the status frame
is transmitted.
Microprocessor Interface
D[7:0]
Microprocessor Data
Input/Output
These pins are inputs when either CS or WR are LOW.
They are outputs when CS and RD are LOW. Other-
wise, these pins are high impedance.
CS
Chip Select
Input, Active LOW
This pin enables the IMR2 device to read from or write
to the microprocessor data bus.
C/D
Control/Data
Input
This pin is used to select either a control register or a
data register in the IMR2 device and is normally con-
nected to the least significant bit of the address bus.
RD
Read Strobe
Input, Active LOW
Initiates read operation.
WR
Write Strobe
Input, Active LOW
Initiates write operation.
RDY
Ready
Output, Active HIGH, Open Drain
RDY is driven LOW at the start of every READ or
WRITE cycle. RDY is released when the IMR2 device
is ready to complete the transaction.
INT
Interrupt
Output, Active LOW, Open Drain
The Interrupt pin is driven LOW when any of the un-
masked (enabled) interrupts occur.
LED Interface
LD[7:0]
LED Drivers
Output
LD is the status output and is transmitted as 2 bytes.
The byte number (high or low) is determined by BSEL.
BSEL
Byte Select
P R E L I M I N A R Y
Am79C983A
Output
When BSEL is LOW, LD[7:0] is transmitting the status
of the first eight PAUI ports (ports P
BSEL is HIGH, LD[7:0] is transmitting the status of the
rest of the PAUI ports (ports P
port, the RAUI port, and the expansion bus.
CRS
Carrier Sense Strobe
Output
When CRS is HIGH, LD [7:0] has carrier sense status.
COLX
Collision Status
Output
When COLX is HIGH, LD [7:0] has collision status.
PART
Partitioning Status
Output
When PART is HIGH, LD [7:0] has partitioning status.
LINK
Link Status
Output
When LINK is HIGH, LD [7:0] has link status.
POL
Polarity Status
Output
When POL is HIGH, LD [7:0] has polarity status.
Miscellaneous Pins
RST
Reset
Input
When RST is LOW, the IMR2 device resets to its
default state.
MCLK
Master Clock
Input
MCLK is a 20-MHz clock input.
Transceiver Device Interface
SDATA [3:0]
Serial Data
Input/Output
SDATA carries command and status data between the
IMR2 device and the QuIET device (or other
connected transceiver).
Pin
SDATA [0]
SDATA [1]
SDATA [2]
SDATA [3]
Transceiver Ports
PAUI [3:0]
PAUI [7:4]
PAUI [11:8]
Arbitrary ports
11
through P
7
through P
8
), the AUI
0
). When
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