AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 34

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

Pn/AUI/RAUI/EP
Note: This function is useful for mapping stations to
ports in a network.
Data Rate Mismatch Interrupt
Address:
A bit is set when the data received by the corresponding
port has caused an overflow or underflow of the FIFO.
This bit is not set unless the received packet, after SFD, is
at least 512 bits long and collision did not occur
Pn/AUI/RAUI/EP
Transceiver Interface Status
Address:
If a QuIET transceiver is not hardware connected, the
corresponding bit on the register is set.
Qn
Transceiver Interface Change Interrupt
Address:
If the device changes from a QuIET device to another type
of transceiver or from a non-QuIET device to a QuIET
device, the corresponding bit on the register is set.
QuIET 0 (Q0)PAUI [3:0]
Qn
34
Byte 0
Byte 1
X
MSB
X
MSB
D Port Read
D Port Read
QuIET 0 (Q0)
QuIET 1 (Q1)
QuIET 2 (Q2)
QuIET 3 (Q3)
QuIET 1 (Q1)
QuIET 2 (Q2)
QuIET 3 (Q3)
D Port Read
MSB
X
X
P7
0
0 QuIET device is connected
1 Non-QuIET transceiver is connected
0
1
1110 1010
1110 1111
1111 0000
P6
EP
No change of transceiver type
Change of transceiver type
X
X
1
0
1
0
P5
RAUI
PAUI [3:0]
PAUI [7:4]
PAUI [11:8]
AUI and RAUI ports
PAUI [7:4]
PAUI [11:8]
AUI and RAUI ports
X
X
Source Address Match Register
No error
Data rate error
No match
Source address matches the
P4
AUI P11 P10 P9
Q3
Q3
P3
Q2
Q2
P2
Q1
Q1
P R E L I M I N A R Y
P1
Q0
Q0
LSB
LSB
P0
P8
LSB
Am79C983A
Byte 0
Byte 1
Jabber Interrupt
Address:
A bit on this register is set if the transceiver connected
to the corresponding port detects jabber.
TPn/SPn
Register Bank 2: Interrupt Control Registers
These registers are accessed by writing the bit pattern
0000 0010 to the C Register. All registers can be read
from as well as written to. A set (1) control bit enables
an interrupt or function of the corresponding port. All
control registers are cleared upon reset. Also, all inter-
rupts are disabled and all status bits are cleared upon
hardware reset.
Partition Status Change Interrupt Enable
Address:
This register is used to enable or mask interrupts
caused by a change in the Port Partitioning Status.
Note that if this is the only cause for the interrupt, dis-
abling an active interrupt source causes the INT output
to be placed into an inactive state. Software should be
designed to write zeros into unused bits.
Pn/AUI/RAUI
Runts with Good FCS Interrupt Enable
Address:
This register is used to enable or mask interrupts
caused by a port receiving a packet that is less than 64
octets (not including preamble and SFD), but is other-
wise well formed and error free.
Byte 0
Byte 1
Byte 0
Byte 1
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3 SP2 SP1 SP0
MSB
D Port Read
D Port Read/Write
D Port Read/Write
P7
0
MSB
P7
0
MSB
1111 0001
1110 0000
1110 0001
P6
0
P6
EP
1
0
0
1
P5
RAUI
P5
RAUI
masked (disabled)
Interrupt enabled
Partition Status Change Interrupt
Partition
Port does not jabber
Port in jabber
P4
AUI P11 P10 P9
P4
AUI P11 P10 P9
TP11 TP
P3
P3
Status
P2
P2
10
TP9 TP8
P1
P1
Change
LSB
P0
P8
P0
P8
LSB
LSB