AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 37

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

Byte 0
Byte 1
Register Bank 3: Port Control Registers
These registers are accessed by writing the bit pattern
0000 0011 into the C register. All registers can be read
from as well as written to.
Alternative Reconnection Algorithm Enable
Address:
The AUI Partitioning/Reconnection state machine can
be programmed for the alternative reconnection algo-
rithm (transmit only). On reset, this register defaults to
the standard reconnection algorithm.
Pn/AUI/RAUI
Link Test Enable
Address
Setting a bit in this register enables the Link Test func-
tion for the corresponding port. This is only in effect
when the IMR2 device is interfaced to a QuIET device.
On reset, this register defaults to Link Test Enabled.
TPn/SPn
Link Pulse Transmit Enable
Address:
Setting a bit in this register enables the corresponding port
to transmit a Link Test Pulse. This is only in effect when the
IMR2 device is interfaced to a QuIET device. On reset, this
register defaults to Link Test Pulse Transmit enabled.
TPn/SPn
Automatic Receiver Polarity Reversal Enable
Address
Setting a bit in this register enables the QuIET device to
automatically invert the receive signal following detec-
tion of the first packet with inverted polarity. This is done
Byte 0
Byte 1
Byte 0
Byte 1
TP7 TP6
SP3 SP2 SP1 SP0
MSB
TP7
SP3 SP2 SP1 SP0
D Port Read/Write
D Port Read/Write
D Port Read/Write
MSB
P7
0
1110 0000
1110 0010
1110 0011
1110 0100
TP6
P6
0
0 Standard Reconnection Algorithm
1 Alternative Reconnection Algorithm
0 Link Test Function disabled
1 Link Test Function enabled
TP5 TP4 TP3 TP2 TP1 TP0
0
1
TP5 TP4 TP3 TP2 TP1 TP0
P5
RAUI
Link Test Pulse Transmit disabled
Link Test Pulse Transmit enabled
P4
AUI P11 P10 P9
TP11 TP
TP11 TP
P3
P2
10
10
TP9 TP8
TP9 TP8
P R E L I M I N A R Y
P1
LSB
P0
P8
LSB
Am79C983A
Byte 0
Byte 1
once after reset or link fail. On reset, this register de-
faults to Automatic Receiver Polarity Reversal disabled.
TPn/SPn
SQE Mask Enable
Address:
Setting a bit in this register allows the corresponding
port to ignore activity on CI during the SQE test window
following a transmission on that port. The SQE test win-
dow is defined by ANSI/IEEE 802.3, Section 7.2.2.2.4
as 6-bit times to 31-bit times following the end of the
packet. Note that the SQE Mask does not affect report-
ing SQE tests on the SQE Status Register and the
SQE Test Change Interrupt Register. On reset, this reg-
ister defaults to SQE Test Mask disabled.
Pn/AUI/RAUI
Port Enable/Disable
Address 1110 0110
Setting a bit in this register enables the corresponding
port. On reset, the ports default to enabled.
Pn/AUI/RAUI
Setting the EP bit will not disable the expansion bus.
However, if the EP bit is not set, data carried on the ex-
pansion bus that is addressed to a MAC will not be
counted in the MIB attributes.
Port Switching Control
Address:
Setting a bit in this register isolates the corresponding
port. All input signals to the corresponding port and all
information concerning port activity from the transceiver
Byte 0
Byte 1
Byte 0
Byte 1
MSB
TP7
SP3 SP2 SP1 SP0
D Port Read/Write
MSB
MSB
D Port Read/Write
D Port Read/Write
P7
0
P7
0
1110 0101
1110 0111
TP6
P6
0
P6
EP
0
1
TP5 TP4 TP3 TP2 TP1 TP0
0
1
0
1
P5
RAUI
P5
RAUI
SQE Test Mask disabled
SQE Test Mask enabled
Disable the corresponding port
Enable the corresponding port
Automatic
Reversal enabled
Automatic
Reversal disabled
P4
AUI P11 P10 P9
P4
AUI P11 P10 P9
TP11 TP
P3
P3
Receiver
Receiver
P2
P2
10
TP9 TP8
P1
P1
Polarity
Polarity
LSB
P0
P8
LSB
P0
P8
LSB
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