AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 32

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

Repeater Device and Revision Register
Address:
This is a read only register. The 8-bit quantity read has
the following format:
D
V
Device Configuration
Address:
This is a read/write register. When this register is writ-
ten, zeros must be written into unassigned fields. The
8-bit quantity has the following format:
R
M
A
Register Bank 1: Interrupts
When a bit on an interrupt register is set, the interrupt
bit on the Status Register is set and the INT pin is
driven. These registers are accessed by writing the bit
32
R
D Port Read/Write
MSB
D3
D Port Read
MSB
Device Type. These bits contain the IMR2
device code.
Revision Number. These bits contain the revision
Repeater Reset. Setting Bit R resets the registers,
repeater, and MAC engine. It is the functional
equivalent of hardware reset, with the exception
that the microprocessor interface is not reset and
the ability to access RMON and port attribute reg-
isters is maintained.
This bit configures the RAUI port. The configura-
tion options are:
D3-0
number. Software may interrogate these bits to de-
termine additional features that may be available
with future versions of the device.
Management Reset. Setting this bit causes the
MAC engine to be reset. When the M bit is set, the
IMR2 device still functions as a repeater, however
MIB tracking is disabled. Setting this bit also allows
the RMON registers and the attribute registers to
be preset by software.
V3-0 0000
0
1
M
D2
M
0
1 to 15
1111 1100
1111 1101
Normal Mode. The RAUI port is configured
Reverse Mode. RCI is an output, i.e., RCI
generates a 10-MHz signal during a collision.
as a standard AUI port.
X3-X0
A
D1
0
D0
Transceiver
QuIET Device ID
Reserved
0010
Revision 0
0
V3
0
V2
IMR2
0
V1
P R E L I M I N A R Y
0
V0
LSB
LSB
Am79C983A
pattern 0000 0001 to the C Register. These registers
are read only and are cleared to 0 upon reading. When
all the interrupt registers are clear (all bits zero), the In-
terrupt bit of the Status Register and INT are cleared.
Note that for each interrupt register there is a corre-
sponding interrupt enable register. The bits on the inter-
rupt register cannot set unless the corresponding bits
on the corresponding interrupt enable register are set.
Port Partition Status Change Interrupt
Address:
Any port changing state between partitioned and re-
connected causes the appropriate register bit to be set
to 1.
The format is as follows:
Pn/AUI/RAUI
Runts with Good FCS Interrupt
Address:
Any port receiving a packet that is less than 64 octets
(not including preamble and SFD), but is otherwise well
formed and error free, causes the appropriate bit to be
set. The format is as follows:
Pn/AUI/RAUI/EP
Link Status Change Interrupt
Address:
A change in the Link Test state of a twisted pair port
associated with a repeater port (from fail to pass or pass
to fail) causes the appropriate bit to be set in this register.
This register is only valid when a QuIET device is
connected to the corresponding port(s).
Byte 0
Byte 1
Byte 0
Byte 1
Byte 0
Byte 1
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
SP3
MSB
D Port Read
MSB
MSB
D Port Read
D Port Read
P7
0
P7
0
1110 0000
1110 0001
1110 0010
SP2
P6
0
P6
EP
0
1
SP1 SP0
1
P5
RAUI
P5
RAUI
0
Partition status of corresponding
Partition status of corresponding
port unchanged
port changed
No runts with valid FCS
Runt with valid FCS
P4
AUI P11 P10 P9
P4
AUI P11 P10 P9
TP11 TP
P3
P3
P2
P2
10
TP9 TP8
P1
P1
P0
P8
P0
P8
LSB
LSB
LSB