AM79C983AKCW AMD [Advanced Micro Devices], AM79C983AKCW Datasheet - Page 22

• Manufacturer Part Number: AM79C983AKCW
• Manufacturer: AMD [Advanced Micro Devices]

Detailed Functions
This section describes the detailed functional behavior
of the IMR2 device. Where necessary, the behavior is
defined in terms of state machines. Note that this is a
conceptual definition and the actual implementation
may be different.
Reset
Hardware Reset
The IMR2 device enters the reset state when the RST
pin is driven LOW. The reset pin should be held LOW
for a minimum of 150 s after power-up or 4 s other-
wise. This allows the IMR2 device to reset the internal
logic. During reset, the registers are set to their default
values. The output signals are placed in their inactive
state. That is, all analog outputs are placed in their idle
state, all bidirectional signals are not driven, all active-
HIGH signals are driven LOW, and all active-LOW sig-
nals are driven HIGH. The only exception is POL, which
defaults to HIGH on reset. In a multiple IMR2 device re-
peater, the reset signal should be synchronized to
MCLK when the expansion bus is operated in the syn-
chronous mode.
Reset does not affect the RMON registers (Register Bank
5) or the Port Attribute Registers (Register Banks 16-30).
These registers will power up at a random value. They
can be preset while the IMR2 is in software reset or while
the port is disabled via the microprocessor interface.
The mode of the expansion bus and the default state of
the ports are set by XMODE and XENA during RST.
XMODE sets the expansion bus mode and XENA sets
the port state. Note that XENA only controls the default
state. Once reset is completed, the enabling and dis-
abling of the ports is under software control. The settings
are as follow:
Software Reset
The IMR2 device supports software reset with two bits
on the Device Configuration Register: Repeater Reset
(R - bit 7 on the register) and Management Reset (M - bit
6 on the register). Bit R resets the registers, repeater,
and MAC engine. Setting Bit R is the functional equiva-
lent of hardware reset, with the exception that the micro-
22
XMODE
XENA
1
0
1
0
The expansion bus is in the asynchronous
(IMR2) mode.
The expansion bus is in the synchronous
(IMR/IMR+) mode.
All ports are enabled.
All PAUI ports are disabled. The output
drivers are placed in a high impedance
state.
P R E L I M I N A R Y
Am79C983A
processor interface is not reset and the ability to access
4 and 6 byte attribute registers is maintained. Bit M af-
fects only the management and intrusion protection
functions of the IMR2 device.
Bit R causes the IMR2 device to go into the default
state. As with hardware reset, all analog outputs are
placed in their idle state, all bidirectional signals are not
driven, all active-HIGH signals are driven LOW, and all
active-LOW signals are driven HIGH. The only excep-
tion is POL, which defaults to HIGH on reset. Registers
are also set to their default state.
Setting Bit R also allows write access to the MIB regis-
ters and some other read-only registers. These regis-
ters are the Total Octets Register, the Transmit Collision
Register, the entire RMON Register Bank, and the Port
Attribute Register Banks. Note that the Last Source Ad-
dress Register and the Preferred Source Address Reg-
ister can also be written into when bit R is not set.
Setting bit R will not affect any bit of the Device Config-
uration Register. Thus, the IMR2 device does not auto-
matically exit software reset. Software reset must be
exited by setting bit R to zero.
The function of bit M is a subset of the function of bit R.
It affects the intrusion protection and MIB registers. Set-
ting bit M causes the intrusion protection registers to go
into the default state. As with bit R, the MIB registers can
be written into. 2 lists the default state of the registers. If
the M column has an M, the corresponding register is set
to its default state when bit M is set.
Expansion Bus
The expansion bus has two modes of operation: the
synchronous (IMR/IMR+ compatible) mode and the
asynchronous mode. The modes are differentiated by
the expansion bus clock. In the synchronous mode, the
IMR2 devices (and any IMR/IMR+ devices) are all
clocked by a single 20-MHz clock. The IMR2 device
uses MCLK as the clock source.
In the asynchronous mode, IMR2 devices can be
clocked (MCLK) by different sources. The single IMR2
device transmitting over the expansion bus provides
the clock source for data. The clock pin in this mode is
ECLK. ECLK clocks the data. All other expansion bus
signals are asynchronous. The mode of expansion bus
operation is selected during reset by XMODE.
The expansion bus can be configured for connection to
a MAC. The pin MACEN selects the MAC mode. When
MACEN is TRUE (LOW), the statistics on the data re-
ceived by DAT are recorded in the management regis-
ters. The expansion bus is considered another port in
the same sense as the PAUIs, the AUI, and the RAUI.