W6691CD WINBOND [Winbond], W6691CD Datasheet - Page 25

• Manufacturer Part Number: W6691CD
• Description: ISDN S/T Interface Transceiver
• Manufacturer: WINBOND [Winbond]

7.2.2 Receiver Clock Recovery And Timing Generation
1) TE mode
stream in TE mode application. This DPLL uses a 7.68 MHz clock as reference. According to I.430, the
transmit clock is normally delayed by 2 bit time from the receive clock. The "total phase deviation from input to
output" is -7% to +15% of a bit period. In some cases, delay compensation may be needed to meet this
requirement (see OPS1-0 bits in D_CTL register).
2) LT-T mode
clock(192KHz) from the received data stream.W6691 generates a CP (Clock Pulse ) derived
192KHz receiving clock with DPLL. CP clock rate is 512KHz or 1536KHz. If CP clock is used to synchronize
NT2 clock, W6691 provide a slip buffer to avoid slipping between DCL and CP.
3) LT-S mode
received data stream. This DPLL uses a 7.68 MHz clock as reference.
This is also the default setting.
specification.
In LT-S modes, A Digital Phase Locked Loop (DPLL) circuit is used to derive the receiving clock from the
A Digital Phase Locked Loop (DPLL) circuit is used to derive the receiving clock from the received data
In LT-T mode application, A Digital Phase Locked Loop (DPLL) circuit is also used to derive the receiving
W6691 does not need RC filter on receiver side, therefore zero delay compensation is selected normally.
The PCM output clocks (PFCK1-2, PBCK) are locked to the S-interface timing with jitter. See the electrical
TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE
OPS1
0
0
1
1
OPS0
0
1
0
1
Effect
No phase delay compensation
Phase delay compensation 260 ns
Phase delay compensation 520 ns
Phase delay compensation 1040 ns
25
Preliminary W6691
Publication Release Date: Sep 2001
Revision 1.1
from the