W6691CD WINBOND [Winbond], W6691CD Datasheet - Page 59

• Manufacturer Part Number: W6691CD
• Description: ISDN S/T Interface Transceiver
• Manufacturer: WINBOND [Winbond]

8.7.2 D_ch transmit FIFO
The D_XFIFO has a length of 64 bytes.
After an D_XFR interrupt, up to 32 bytes of data can be written into this FIFO for transmission. At the first time
transmission, up to 64 bytes of data can be written.
8.7.3 D_ch command register
Value after reset: 00H
RACK
to acknowledge the interrupt. Writing “0” to this bit has no effect. If RACK bit is set to “1” for operating
“Receiver Acknowledge”, It is not necessary to reset RACK bit to “0” by host processor. That is to say, once
RACK is set to “1”, RACK bit is reset to “0” by W6691 automatically.
RRST
effect. If RRST bit is set to “1” for operating “Receiver Reset”, It is not necessary to reset RRST bit to “0” by
host processor. That is to say, once RRST is set to “1”, RRST bit is reset to “0” by W6691 automatically.
STT1
TIMR1 register. Writing “0” to this bit has no effect. If SST1 bit is set to “1” for operating “Start Timer1”, It is not
necessary to reset STT1 bit to “0” by host processor. That is to say, once STT1 is set to “1”, STT1 bit is reset
to “0” by W6691 automatically.
RACK
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data. Writing “0” to this bit has no
The timer 1 is started when this bit is set to one. The timer is stopped when it expires or by a write of the
7
Start Timer 1
Receiver Reset
Receive Acknowledge
RRST
6
5
0
STT1
4
XMS
D_XFIFO
D_CMDR
3
2
0
59
Write Address 01H
Write
XME
1
XRST
0
Address 02H
Preliminary W6691
Publication Release Date: Sep 2001
Revision 1.1