W6691CD WINBOND [Winbond], W6691CD Datasheet - Page 89

• Manufacturer Part Number: W6691CD
• Description: ISDN S/T Interface Transceiver
• Manufacturer: WINBOND [Winbond]

Preliminary W6691
In extended transparent mode, setting this bit stops the B1_XFIFO data transmission.
This bit is write-only. It's auto-clear.
XRST
Transmitter Reset
Setting this bit resets the B1_ch HDLC transmitter and clears the B1_XFIFO. The transmitter will send inter
frame time fill pattern on B channel in transparent mode, or idle pattern in extended transparent mode. This
command also results in a transmit FIFO ready condition.
This bit is write only. It's auto-clear.
8.11.4 B1_ch Mode Register
B1_MODE
Read/Write
Address
54H
Value after reset: 00H
7
6
5
4
3
2
1
0
MMS
ITF
RACT
XACT
B1_128K
SW56
FTS1
FTS0
MMS
Message Mode Setting
Determines the message transfer modes of the B1_ch HDLC controller:
0: Transparent mode. In received direction, address comparison is performed on each frame. The frames with
matched address are stored in B1_RFIFO. Flag deletion, CRC check and zero bit deletion are performed. In
transmitted direction, the data is transmitted with flag insertion, zero bit insertion and CRC generation.
1: Extended transparent mode. In received direction, all data are received and stored in the B1_RFIFO. In
transmitted direction, all data in the B1_XFIFO are transmitted without alteration.
ITF
Inter-frame Time Fill
Defines the inter-frame time fill pattern in transparent mode.
0 : Mark. The binary value "1" is transmitted.
1 : Flag. This is a sequence of "01111110".
RACT
Receiver Active
"1": transmitter is active, 64 KHz clock is provided.
"0": transmitter is inactive, clock is LOW to save power.
This bit is read/write. Read operation returns the previously written value.
Note: The receiver is deactive after hardware reset or software reset.
Publication Release Date: Sep 2001
89
Revision 1.1