W6691CD WINBOND [Winbond], W6691CD Datasheet - Page 88

• Manufacturer Part Number: W6691CD
• Description: ISDN S/T Interface Transceiver
• Manufacturer: WINBOND [Winbond]

When the number of empty locations is equal to or greater than the threshold value, a XFR interrupt is
generated. After a XFR interrupt, up to 64 or 96 bytes of data can be written into this FIFO for transmission.
8.11.3 B1_ch command register
Value after reset: 00H
RACK
After a RMR or RME interrupt, the microprocessor reads out the data in B1_RFIFO, it then sets this bit to
explicitly acknowledge the interrupt.
This bit is write only. It's auto-clear. Writing “0” to this bit has no effect. If RACK bit is set to “1” for operating
“Receiver Acknowledge”, It is not necessary to reset RACK bit to “0” by host processor. That is to say, once
RACK is set to “1”, RACK bit is reset to “0” by W6691 automatically.
RRST
Setting this bit resets the B1_ch HDLC receiver.
This bit is write-only. It's auto-clear. Writing “0” to this bit has no effect. If RRST bit is set to “1” for operating
“Receiver Reset”, It is not necessary to reset RRST bit to “0” by host processor. That is to say, once RRST is
set to “1”, RRST bit is reset to “0” by W6691 automatically.
XMS
In transparent mode, setting this bit initiates the transparent transmission of B1_XFIFO data. The opening flag
is automatically added to the message by the B1_ch HDLC controller. Zero bit insertion is performed on the
data. This bit is also used in subsequent transmission of the frame.
In extended transparent mode, settint this bit activates the transmission of B1_XFIFO data. No flag, CRC or
zero bit insertion is added on the data.
This bit is write-only. It's auto-clear. Writing “0” to this bit has no effect. If XMS bit is set to “1” for operating
“Transmit Message Start/Continue”, It is not necessary to reset XMS bit to “0” by host processor. That is to
say, once XMS is set to “1”, XMS bit is reset to “0” by W6691 automatically.
XME
In transparent mode, setting this bit indicates the end of the whole frame transmission. The B1_ch HDLC
controller transmits the data in FIFO and automatically appends the CRC and the closing flag sequence in
transparent mode.
RACK
7
Transmit Message Start/Continue
Transmit Message End
Receiver Reset
Receive Message Acknowledge
RRST
6
5
0
0
4
B1_CMDR
3
0
XMS
2
88
Read/Write
XME
1
XRST
0
Address 53H
Preliminary W6691
Publication Release Date: Sep 2001
Revision 1.1