W6691CD WINBOND [Winbond], W6691CD Datasheet - Page 91

• Manufacturer Part Number: W6691CD
• Description: ISDN S/T Interface Transceiver
• Manufacturer: WINBOND [Winbond]

RMR
At least a threshold lenth of data has been stored in the B1_RFIFO.
RME
Used in transparent mode only. The last block of a frame has been received. The frame length can be found in
B1_RBCH + B1_RBCL registers. The number of data available in the B1_RFIFO equals frame lenth modulus
threshold. The result of CRC check is indicated by B1_STAR:CRCE bit.
When the number of last block of a frame equals the threshold, only RME interrupt is generated.
RDOV
Data overflow occurs in the receive FIFO. The incoming data will overwrite the data in the receive FIFO.
XFR
This interrupt indicates that up to a threshold length of data can be written into the B1_XFIFO.
XDUN
This interrupt occurs when the B1_XFIFO has run out of data. In this case, the W6691 will automatically reset
the transmitter and send the inter frame time fill pattern on B channel. The software must wait until transmit
FIFO ready condition (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
8.11.6 B1_ch Extended Interrupt Mask Register
Value after reset: FFH
Setting the bit to "1" masks the corresponding interrupt source in B1_EXIR register. Masked interrupt status
bits are read as zero when B1_EXIR register is read. They are internally stored and pending until the mask bits
are zero.
All the interrupts in B1_EXIR will be masked if the IMASK : B1_EXI bit is set to "1".
8.11.7 B1_ch Status Register
Value after reset: 20H
7
1
7
0
Receive Message End
Receive Message Ready
Transmit FIFO Ready
Transmit Data Underrun
Receive Data Overflow
RDOV
RMR
6
6
CRCE
RME
5
5
RDOV
RMB
4
4
B1_STAR
3
1
3
0
XDOW
2
1
2
Read
91
B1_EXIM
XFR
1
1
0
Address 58H
XDUN
XBZ
0
0
Read/Write
Preliminary W6691
Publication Release Date: Sep 2001
Address 57H
Revision 1.1