W6691CD WINBOND [Winbond], W6691CD Datasheet - Page 6

• Manufacturer Part Number: W6691CD
• Description: ISDN S/T Interface Transceiver
• Manufacturer: WINBOND [Winbond]

Preliminary W6691
TABLE 8.5 GCI BUS REGISTER MEMORY MAP ............................................................................... 57
TABLE 8.7 B1 CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................. 86
TABLE 8.8 B1 CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP ................................... 87
TABLE 8.9 B2 CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................. 95
TABLE 8.10 B2 CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP ................................. 95
LIST OF TABLES
TABLE 7.1 OUTPUT PHASE DELAY COMPENSATION TABLE ........................................................ 25
TABLE 7.2 LAYER 1 COMMAND CODES ........................................................................................... 28
TABLE 7.3 LAYER 1 INDICATION CODES ......................................................................................... 28
TABLE 7.4 LAYER 1 COMMAND CODES ........................................................................................... 33
TABLE 7.5 LAYER 1 INDICATION CODES ......................................................................................... 33
TABLE 7.8 D PRIORITY CLASSES ..................................................................................................... 35
TABLE 7.9 D PRIORITY COMMANDS/INDICATIONS ........................................................................ 35
TABLE 7.10 MULTIFRAME STRUCTURE IN S/T INTERFACE .......................................................... 39
TABLE 8.1 D CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................... 53
TABLE 8.2 GCI BUS CONTROL REGISTER ADDRESS MAP ........................................................... 54
TABLE 8.3 MISCELLANEOUS REGISTER ADDRESS MAP .............................................................. 55
TABLE 8.4 D CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP..................................... 55
TABLE 8.5 GCI BUS REGISTER MEMORY MAP ............................................................................... 57
TABLE 8.7 B1 CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................. 86
TABLE 8.8 B1 CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP ................................... 87
TABLE 8.9 B2 CHANNEL HDLC CONTROLLER REGISTER ADDRESS MAP.................................. 95
TABLE 8.10 B2 CHANNEL HDLC CONTROLLER REGISTER MEMORY MAP ................................. 95
Publication Release Date: Sep 2001
6
Revision 1.1