AX88172A ASIX [ASIX Electronics Corporation], AX88172A Datasheet - Page 18

• Manufacturer Part Number: AX88172A
• Description: USB 2.0 to 10/100M Fast Ethernet Controller
• Manufacturer: ASIX [ASIX Electronics Corporation]

TXCLK
TXEN
TXD [3:0]
MDC
MDIO
TXCLK
TXEN
TXD [3:0]
CRS
COL
RXER
RXCLK
RXDV
RXD [3:0]
MDC
MDIO
REFCLK_I
O3/PD/T
O3/PD/T
O3/PD/T
O3/PD
B5/PU
B5/PU
I5/PD
I5/PD
I5/PD
I5/PD
O3/T
O3/T
O3/T
O3/T
O3
O3
External Media Interface: PHY Mode with Reverse-RMII Interface
I5
External Media Interface: PHY Mode with Reverse-MII Interface
59, 60,
19, 20,
59, 60,
61, 62
22, 23
61, 62
63
64
44
43
17
18
31
32
34
63
64
44
43
17
Transmit Clock. TXCLK is received from PHY to provide timing
reference for the transfer of TXD [3:0] and TXEN signals on transmit
direction of MII interface.
Transmit Enable. TXEN is asserted high to indicate a valid TXD [3:0]. It is
transitioned synchronously with respect to the rising edge of TXCLK.
Transmit Data. TXD [3:0] is transitioned synchronously with respect to
the rising edge of TXCLK. Note TXD [3:2] are also used as Chip
Operation Mode selection pins; please refer to section
Station management clock output to PHY. All data transferred on MDIO
are synchronized to the rising edge of this clock. The frequency of MDC is
1.5MHz.
Station management data input/output. Serial data input/output transferred
from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII
spec.
Transmit Clock. This clock is provided to supply to the TX_CLK of
externally connected Ethernet MAC device with MII. This pin is tri-stated
in isolate mode.
Transmit enable. TXEN is asserted high to indicate a valid TXD [3:0]. It
should be driven synchronously with respect to the rising edge of TXCLK
by the externally connected Ethernet MAC device with MII.
Transmit Data. TXD [3:0] should be driven synchronously with respect to
the rising edge of TXCLK by the externally connected Ethernet MAC
device with MII.
Carrier Sense. CRS is asserted high by AX88172A when RXDV is
asserted high in Reverse-MII mode. This pin is tri-stated in isolate mode.
Collision. COL is always driven low because AX88172A is operating in
100M/full-duplex mode internally in Reverse-MII mode. This pin is
tri-stated in isolate mode.
Receive Error. RXER is always driven low by AX88172A in Reverse-MII
mode. This pin is tri-stated in isolate mode.
Receive clock. This clock is provided to supply to the RX_CLK of
externally connected Ethernet MAC device with MII. This pin is tri-stated
in isolate mode.
Receive Data Valid. RXDV is asserted high when valid data is present on
RXD [3:0]. It is transitioned synchronously with respect to RXCLK from
AX88172A to the externally connected Ethernet MAC device with MII.
This pin is tri-stated in isolate mode.
Receive Data. RXD [3:0] is transitioned synchronously with respect to
RXCLK from AX88172A to the externally connected Ethernet MAC
device with MII. Note that RXD [3:2] are also used as Chip Operation
Mode selection pins. Please refer to section
tri-stated in isolate mode.
Station Management clock input from the externally connected Ethernet
MAC device. All data transferred on MDIO are synchronized to the rising
edge of this clock.
Station Management Data. Serial data input/output transferred from/to the
externally connected MAC device. The transfer protocol should conform
to the IEEE 802.3u MII spec.
50Mhz +/-50ppm Reference clock input for RMII receive, transmit and
control signals. If externally connected Ethernet MAC device with RMII
can’t provide 50Mhz Reference clock to AX88172A, then user can
connect this pin to REFCLK_O and use REFCLK_O to supply clock to
the externally connected Ethernet MAC device at the same time.
USB 2.0 to 10/100M Fast Ethernet Controller
18
ASIX ELECTRONICS CORPORATION
AX88772A/AX88172A
2.3 Settings.
Low-pin-count
2.3 Settings.
These pins are