AX88172A ASIX [ASIX Electronics Corporation], AX88172A Datasheet - Page 35

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AX88172A

Manufacturer Part Number
AX88172A
Description
USB 2.0 to 10/100M Fast Ethernet Controller
Manufacturer
ASIX [ASIX Electronics Corporation]
Datasheet

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Note: Above diagram only shows setup and hold time relationship of SPI pins in Mode 0. For the remaining 3 modes,
clock polarity is reversed.
Fclk
Tl
Th
Tdly
Dsu
Dhd
tl
Symbol
SPI Master Controller Timing Table:
Note 3: Fsys_clk is the operating system clock frequency 30Mhz. The SPIBRR is SPI Baud Rate Register.
Note 4: Tsys_clk =1/ Fsys_clk =33.33 ns.
Note 5: It will be much greater than 22us because several factors can influence this parameter, such as USB system
9.4.9 SPI Interface Timing
Tclk = 1/Fclk.
utilization, the CBW structure, and High/Full speed ,etc.
SPI_SCLK clock frequency.
Setup time of SPI_SS to the first SPI_SCLK edge.
Hold time of SPI_SS after the last SPI_SCLK edge.
SPI_MOSI data valid time after SPI_SCLK edge.
SPI_MISO data setup time before SPI_SCLK edge.
SPI_MISO data hold time after SPI_SCLK edge.
Minimum idle time between transfers (minimum
SPI_SS high time).
Internal time base period.
Description
USB 2.0 to 10/100M Fast Ethernet Controller
35
Min
2
4
-
-
-
-
-
(SPIBRR+1)*2
Fsys_clk/
ASIX ELECTRONICS CORPORATION
Typ
0.5
0.5
0.5
AX88772A/AX88172A
-
-
-
Note 5
Max
5
1
Low-pin-count
-
-
-
-
-
(Note 3)
Tsys_clk
Tsys_clk
Tsys_clk
(Note 3)
(Note 4)
MHz
Tclk
Unit
Tclk
Tclk

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