DM74S257N Fairchild Semiconductor, DM74S257N Datasheet

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DM74S257N

Manufacturer Part Number
DM74S257N
Description
IC SELECTOR/MUX QD 2-1LINE 16DIP
Manufacturer
Fairchild Semiconductor
Series
74Sr
Type
Data Selector/Multiplexerr
Datasheet

Specifications of DM74S257N

Circuit
4 x 2:1
Independent Circuits
1
Current - Output High, Low
6.5mA, 20mA
Voltage Supply Source
Single Supply
Voltage - Supply
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74S257
74S257N

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© 2000 Fairchild Semiconductor Corporation
DM74S257N
DM74S257
3-STATE Quad 1-of-2 Data Selector/Multiplexer
General Description
These Schottky-clamped high-performance multiplexers
feature 3-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a HIGH or LOW logic level. To minimize the pos-
sibility that two outputs will attempt to take a common bus
to opposite logic levels, the output enable circuitry is
designed such that the output disable times are shorter
than the output enable times.
This 3-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL reg-
isters for data retention throughout the system.
Ordering Code:
Connection Diagram
Order Number
Package Number
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006482
Features
Function Table
H
L
X
Z
3-STATE versions S157, S158, with same pin-outs
Schottky-clamped for significant improvement in
A-C performance
Provides bus interface from multiple sources in high-per-
formance systems
Average propagation delay from data input
Typical power dissipation
LOW Level
Don’t Care
High Impedance (OFF)
HIGH Level
Control
Output
Package Description
H
L
L
L
L
Select
X
H
H
L
L
Inputs
August 1986
Revised May 2000
A
X
H
X
X
L
www.fairchildsemi.com
B
H
X
X
X
L
320 mW
4.8 ns
Output
Y
Z
H
H
L
L

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DM74S257N Summary of contents

Page 1

... It also permits the use of standard TTL reg- isters for data retention throughout the system. Ordering Code: Order Number Package Number DM74S257N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 4

Switching Characteristics 5V and Symbol Parameter t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...

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