S9S12GA192F0MLHR Freescale Semiconductor, S9S12GA192F0MLHR Datasheet - Page 513

• Manufacturer Part Number: S9S12GA192F0MLHR
• Description: 16-bit Microcontrollers - MCU 16BIT192KFLASH 11264 RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GA192F0MLHR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

14.3.2.10 ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
14.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x000C
Module Base + 0x000E
CMPHT[11:0]
IEN[11:0]
Reset
Reset
Field
11–0
Field
11–0
W
W
R
R
15
15
1
1
0
0
ATD Digital Input Enable on channel x (x= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input
buffer from the analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
Compare Operation Higher Than Enable for conversion number n (n= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of
a Sequence (n conversion number, NOT channel number!) — This bit selects the operator for comparison
of conversion results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
= Unimplemented or Reserved
= Unimplemented or Reserved
14
14
1
1
0
0
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
Figure 14-13. ATD Compare Higher Than Register (ATDCMPHT)
13
13
1
1
0
0
Figure 14-12. ATD Input Enable Register (ATDDIEN)
12
12
1
1
0
0
Table 14-20. ATDCMPHT Field Descriptions
MC9S12G Family Reference Manual, Rev.1.23
Table 14-19. ATDDIEN Field Descriptions
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Description
Description
0
0
7
7
CMPHT[11:0]
IEN[11:0]
0
0
6
6
Analog-to-Digital Converter (ADC12B12CV2)
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
0
0
0
0
515