S9S12GA192F0MLHR Freescale Semiconductor, S9S12GA192F0MLHR Datasheet - Page 894

• Manufacturer Part Number: S9S12GA192F0MLHR
• Description: 16-bit Microcontrollers - MCU 16BIT192KFLASH 11264 RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GA192F0MLHR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

48 KByte Flash Module (S12FTMRG48K1V1)
1
2
26.3.2.9
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
1
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see
as indicated by reset condition ‘F’ in
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
896
single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data
attempted while command running) is indicated when both SFDIF and DFDIF flags are high.
There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after
a flash memory read before checking FERSTAT for the occurrence of ECC errors.
Loaded from IFR Flash configuration field, during reset sequence.
The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either
Offset Module Base + 0x0008
Reset
DFDIF
SFDIF
Field
1
0
W
R
FPOPEN
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
returning invalid data was attempted on a Flash block that was under a Flash command operation.
flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash
command operation.
SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted
P-Flash Protection Register (FPROT)
F
7
1
running
while command running
RNV6
F
= Unimplemented or Reserved
6
1
Figure 26-13. Flash Protection Register (FPROT)
1
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
Table 26-16. FERSTAT Field Descriptions
MC9S12G Family Reference Manual,
Section 26.3.2.9.1, “P-Flash Protection Restrictions,” and Table
FPHDIS
Figure
F
5
1
26-13. To change the P-Flash protection that will be loaded
F
4
1
FPHS[1:0]
Description
F
3
1
Rev.1.23
FPLDIS
F
2
1
2
Freescale Semiconductor
F
1
1
FPLS[1:0]
Table
1
The DFDIF
26-21).
F
26-4)
0
1