S9S12GA192F0MLHR Freescale Semiconductor, S9S12GA192F0MLHR Datasheet - Page 872

• Manufacturer Part Number: S9S12GA192F0MLHR
• Description: 16-bit Microcontrollers - MCU 16BIT192KFLASH 11264 RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GA192F0MLHR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 192 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT

32 KByte Flash Module (S12FTMRG32K1V1)
25.4.7
The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.
25.4.7.1
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to
(FCNFG)”,
Status Register
The logic used for generating the Flash module interrupts is shown in
874
Flash Command Complete
ECC Double Bit Fault on Flash Read
ECC Single Bit Fault on Flash Read
Section 25.3.2.6, “Flash Error Configuration Register
Interrupts
Description of Flash Interrupt Operation
Vector addresses and their relative interrupt priority are determined at the
MCU level.
(FSTAT)”, and
Interrupt Source
DFDIE
DFDIF
SFDIE
SFDIF
CCIE
CCIF
Figure 25-27. Flash Module Interrupts Implementation
Section 25.3.2.8, “Flash Error Status Register
MC9S12G Family Reference Manual,
Table 25-66. Flash Interrupt Sources
(FERSTAT register)
(FERSTAT register)
(FSTAT register)
Interrupt Flag
DFDIF
SFDIF
Section 25.3.2.5, “Flash Configuration Register
CCIF
NOTE
Flash Command Interrupt Request
Flash Error Interrupt Request
(FERCNFG register)
(FERCNFG register)
(FCNFG register)
(FERCNFG)”,
Rev.1.23
Local Enable
DFDIE
SFDIE
CCIE
Figure
25-27.
(FERSTAT)”.
Section 25.3.2.7, “Flash
Freescale Semiconductor
Global (CCR)
Mask
I Bit
I Bit
I Bit