DM74S182N Fairchild Semiconductor, DM74S182N Datasheet

DM74S182N

Manufacturer Part Number

DM74S182N

Description

IC GENERATOR LOOK-AHEAD 16-DIP

Manufacturer

Fairchild Semiconductor

Series

74Sr

Datasheet

1.DM74S182N.pdf (5 pages)

Specifications of DM74S182N

Logic Type

Look-ahead Carry Generator

Supply Voltage

4.75 V ~ 5.25 V

Number Of Bits

Operating Temperature

0°C ~ 70°C

Mounting Type

Through Hole

Package / Case

16-DIP (0.300", 7.62mm)

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74S182
74S182N

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DM74S182N

DM74S182

Look-Ahead Carry Generator

General Description

These circuits are high-speed, look-ahead carry genera-

tors, capable of anticipating a carry across four binary

adders or groups of adders. They are cascadable to per-

form full look-ahead across n-bit adders. Carry, generate-

carry, and propagate-carry functions are provided as

shown in the pin designation table.

When used in conjunction with the 181 arithmetic logic unit,

these generators provide high-speed carry look-ahead

capability for any word length. Each DM74S182 generates

the look-ahead (anticipated carry) across a group of four

ALU’s and, in addition, other carry look-ahead circuits may

be employed to anticipate carry across sections of four

look-ahead packages up to n-bits. The method of cascad-

ing circuits to perform multi-level look-ahead is illustrated

under typical application data.

Carry input and output of the ALU’s are in their true form,

and the carry propagate (P) and carry generate (G) are in

negated form; therefore, the carry functions (inputs, out-

Ordering Code:

Connection Diagram

Order Number

Package Number

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006474

puts, generate, and propagate) of the look-ahead genera-

tors are implemented in the compatible forms for direct

connection to the ALU. Reinterpretations of carry functions,

as explained on the 181 data sheet are also applicable to

and compatible with the look-ahead generator. Positive

logic equations for the DM74S182 are:

Features

Pin Designations

G0, G1, G2, G3

Typical propagation delay time 7 ns

Typical power dissipation 260 mW

P0, P1, P2, P3

Designation

P3 P2 P1 P0

G3 (P3

(P3

Package Description

GND

, C

P0 C

P1 G0

P2 G1

G2) (P3

3, 1, 14, 5

4, 2, 15, 6

Pin Nos.

12, 11, 9

G0)

P1 P0 C

P2 P1 G0

August 1986

Revised March 2000

G1)

Carry Propagate Output

Carry Propagate Inputs

Carry Generate Output

Carry Generate Inputs

P2 P1 P0 C

www.fairchildsemi.com

Supply Voltage

Carry Outputs

Active LOW

Carry Input

Function

Ground

Related parts for DM74S182N

DM74S182N Summary of contents

Page 1

... Ordering Code: Order Number Package Number DM74S182N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram © 2000 Fairchild Semiconductor Corporation puts, generate, and propagate) of the look-ahead genera- tors are implemented in the compatible forms for direct connection to the ALU ...

Page 2

Logic Diagram V PIN 16 CC GND PIN 8 Typical Application 64-Bit ALU, Full-Carry Look Ahead in Three Levels A and B inputs, and F outputs of 181 are not shown. www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 4

Switching Characteristics and Symbol Parameter t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...

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