S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 252

• Manufacturer Part Number: S9S12G64F0CLFR
• Description: 16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0CLFR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 40
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

Port Integration Module (S12GPIMV1)
2.6
2.6.1
After a system reset, software should:
GA240 / GA192 devices only:
2.6.2
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
2.6.3
To avoid unintended IRQ interrupts resulting from writing to IRQCR while the IRQ pin is driven to active
level (IRQ=0) the following initialization sequence is recommended:
2.6.4
The ADC external trigger inputs ETRIG3-0 allow the synchronization of conversions to external trigger
events if selected as trigger source (for details refer to ATDCTL1[ETRIGSEL] and ATDCTL1[ETRIGCH]
configuration bits in ADC section). These signals are related to PWM channels 3-0 to support periodic
trigger applications with the ADC. Other pin functions can also be used as triggers.
If a PWM channel is routed to an alternative pin, the ETRIG input function will follow the relocation
accordingly.
If the related PWM channel is enabled, the PWM signal as seen on the pin will drive the ETRIG input. If
another signal of higher priority takes control of the pin or if on a port AD pin the input buffer is disabled,
254
1. Read the PKGCR and write to it with its preset content to engage the write lock on
2. Write to PRR0 in 20 TSSOP to define the module routing and to PKGCR[APICLKS7] bit in any
3. In applications using the analog functions on port C pins shared with AMPM1, AMPP1 or DACU1
1. Mask I-bit
2. Set IRQCR[IRQEN]
3. Set IRQCR[IRQE]
4. Clear I-bit
PKGCR[PKGCR2:PKGCR0] bits protecting the device from inadvertent changes to the pin layout
in normal applications.
package for API_EXTCLK.
the input buffers should be disabled early after reset by enabling the related mode of the DAC1
module. This shortens the time of potentially increased power consumption caused by the digital
input buffers operating in the linear region.
Initialization/Application Information
Initialization
Port Data and Data Direction Register writes
Enabling IRQ edge-sensitive mode
ADC External Triggers ETRIG3-0
MC9S12G Family Reference Manual,
Rev.1.23
Freescale Semiconductor