S9S12G64F0CLFR Freescale Semiconductor, S9S12G64F0CLFR Datasheet - Page 615

• Manufacturer Part Number: S9S12G64F0CLFR
• Description: 16-bit Microcontrollers - MCU S12 Core,64K FLASH AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0CLFR

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 1 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit, 12 bit
• A/d Channels Available: 12
• Interface Type: SPI
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 40
• Number Of Timers: 8
• Program Memory Type: Flash
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.13 V

1
18.3.3.5
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
“MSCAN Control Register 0
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
1
Freescale Semiconductor
Module Base + 0x00XD
Module Base + 0x00XE
Module Base + 0x00XF
Read: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Read: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Unimplemented
Reset:
Reset:
Reset:
W
W
W
R
R
R
Time Stamp Register (TSRH–TSRL)
TSR15
PRIO7
TSR7
0
7
7
x
7
x
Figure 18-37. Time Stamp Register — High Byte (TSRH)
Figure 18-38. Time Stamp Register — Low Byte (TSRL)
Figure 18-36. Transmit Buffer Priority Register (TBPR)
TSR14
PRIO6
TSR6
6
0
6
x
6
x
(CANCTL0)”). In case of a transmission, the CPU can only read the time
MC9S12G Family Reference Manual, Rev.1.23
Section 18.3.2.7, “MSCAN Transmitter Flag Register
Section 18.3.2.7, “MSCAN Transmitter Flag Register
Section 18.3.2.7, “MSCAN Transmitter Flag Register
TSR13
PRIO5
TSR5
0
5
5
x
5
x
TSR12
PRIO4
TSR4
4
0
4
x
4
x
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 18.3.2.11, “MSCAN Transmit Buffer Selection Register
Freescale’s Scalable Controller Area Network (S12MSCANV3)
TSR11
PRIO3
TSR3
0
x
x
3
3
3
TSR10
PRIO2
TSR2
2
0
2
x
2
x
(CANTFLG)”) and the
(CANTFLG)”) and the
(CANTFLG)”) and the
Access: User read/write
Access: User read/write
Access: User read/write
PRIO1
TSR9
TSR1
Section 18.3.2.1,
0
x
x
1
1
1
PRIO0
TSR8
TSR0
0
0
0
x
0
x
617
1
1
1