74LVX161284AMTX Fairchild Semiconductor, 74LVX161284AMTX Datasheet

74LVX161284AMTX

Manufacturer Part Number

74LVX161284AMTX

Description

TXRX TRANSLATING IEEE 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74LVXr

Datasheet

1.74LVX161284AMTD.pdf (9 pages)

Specifications of 74LVX161284AMTX

Logic Type

IEEE STD 1284 Translation Transceiver

Supply Voltage

3 V ~ 3.6 V

Number Of Bits

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

74LVX161284AMTX

Manufacturer:

FAIRCHILD/仙童

Quantity:

20 000

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74LVX161284AMTD

74LVX161284A

Low Voltage IEEE 161284 Translating Transceiver

General Description

The LVX161284A contains eight bidirectional data buffers

and eleven control/status buffers to implement a full

IEEE 1284 compliant interface. The device supports the

IEEE 1284 standard, with the exception of output slew rate,

and is intended to be used in an Extended Capabilities Port

mode (ECP). The pinout allows for easy connection from

the Peripheral (A-side) to the Host (cable side).

Outputs on the cable side can be configured to be either

open drain or high drive ( 14 mA) and are connected to a

separate power supply pin (V

puts to be driven by a higher supply voltage than the

A-side. The pull-up and pull-down series termination resis-

tance of these outputs on the cable side is optimized to

drive an external cable. In addition, all inputs (except HLH)

and outputs on the cable side contain internal pull-up resis-

tors connected to the V

termination and pull-ups for open drain mode.

Outputs on the Peripheral side are standard low-drive

CMOS outputs designed to interface with 3V logic. The DIR

input controls data flow on the A

pins.

Ordering Code

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Package

Number

MTD48

cable supply to provide proper

cable) to allow these out-

–A

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

–B

DS500204

transceiver

Features

Pin Descriptions

DIR

PLH

HLH

Pin Names

Supports IEEE 1284 Level 1 and Level 2 signaling

standards for bidirectional parallel communications

between personal computers and printing peripherals

with the exception of output slew rate

Translation capability allows outputs on the cable side to

interface with 5V signals

All inputs have hysteresis to provide noise margin

B and Y output resistance optimized to drive external

cable

B and Y outputs in high impedance mode during power

down

Inputs and outputs on cable side have internal pull-up

resistors

Flow-through pin configuration allows easy interface

between the “Peripheral and Host”

Replaces the function of two (2) 74ACT1284 devices

–A

–B

–A

–Y

–A

–C

Package Description

High Drive Enable Input (Active HIGH)

Direction Control Input

Inputs or Outputs

Inputs

Outputs

Inputs

Peripheral Logic HIGH Input

Peripheral Logic HIGH Output

Host Logic HIGH Input

Host Logic HIGH Output

June 1999

Revised July 2000

Description

www.fairchildsemi.com

Related parts for 74LVX161284AMTX

74LVX161284AMTX Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Features Supports IEEE 1284 Level 1 and Level 2 signaling ...

Page 2

Logic Symbol Truth Table Inputs DIR Note 1: Y –Y Open Drain Outputs 9 13 Note 2: B –B Open Drain Outputs 1 8 Logic Diagram www.fairchildsemi.com Outputs –B Data to A –A ...

Page 3

Absolute Maximum Ratings Supply Voltage CC—Cable V Must Be V CC—Cable CC Input Voltage (V )—(Note –A , PLH , DIR – –C , ...

Page 4

DC Electrical Characteristics Symbol Parameter V Maximum LOW A , HLH OL n Level Output Voltage PLH PLH R Maximum Output B – – ...

Page 5

AC Electrical Characteristics Symbol Parameter t A – –B PHL – –B PLH – –A PHL ...

Page 6

AC Loading and Waveforms Pulse Generator for all pulses: Rate 1.0 MHz; Z FIGURE 1. t FIGURE 2. t PLHin to PLH FIGURE – www.fairchildsemi.com 2.5 ns, ...

Page 7

AC Loading and Waveforms FIGURE 4. t and t PHZ FIGURE 5. t and t PZH (Continued) Test Load and Waveforms, DIR to A –A PLZ 1 Test Load and Waveforms, DIR to A –A PZL ...

Page 8

AC Loading and Waveforms FIGURE 6. t www.fairchildsemi.com (Continued) and t Test Load and Waveforms PHZ PLZ DIR to B – ...

Page 9

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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