AT49LH002-33JC Atmel, AT49LH002-33JC Datasheet - Page 11

• Manufacturer Part Number: AT49LH002-33JC
• Description: IC FLASH 2MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LH002-33JC

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LPC Memory
Cycles
3377B–FLASH–9/03
A valid LPC memory cycle begins with the host driving the FWH4/LFRAME signal low for one
or more clock cycles. While the FWH4/LFRAME signal is low, a valid START value of 0000b
must be driven on the FWH/LAD[3:0] pins. Following the START field, a CYCTYPE + DIR
(Cycle Type and Direction) field must be sent to the device to indicate the type of cycle (e.g.,
memory access, I/O access, etc.) and the direction (read or write) of the transfer. After the
CYCTYPE + DIR field has been sent, the 8-clock MADDR (Memory Address) field must be
sent to the device to provide the 32-bit starting address location of where to begin reading or
writing in the memory.
Figure 4. LPC Memory Cycle Initiation and Addressing
START FIELD: This 1-clock field indicates the start of a cycle. It is valid on the last clock that
FWH4/LFRAME is sampled low. The start field that is used for an LPC cycle is 0000b. If the
start field that is sampled is not 0000b, then the cycle attempted is not an LPC memory cycle.
It may be a valid FWH memory cycle that the device will attempt to decode.
CYCTYPE + DIR (CYCLE TYPE AND DIRECTION) FIELD: This 1-clock field is used to indi-
cate the type of cycle and the direction of the transfer to be performed. Of the four bits placed
on the FWH/LAD[3:0] pins, bits[3:2] must be 01b to indicate that the transfer will be a memory
cycle. Values other than 01b, which may be used to specify an I/O cycle or a DMA cycle for
other components in the system, will cause the device to enter standby mode when the
FWH4/LFRAME pin is brought high and no internal operation is in progress. The
FWH/LAD[3:0] pins will also be placed in a high-impedance state.
Bit[1] is used to determine the direction of the transfer. 0 is used to indicate a read, and 1 is
used to indicate a write. Bit[0] is ignored and reserved for future use. Table 6 details the two
valid CYCTYPE + DIR fields that the device will respond to.
Table 6. Valid CYCTYPE + DIR Values
MADDR (MEMORY ADDRESS) FIELD: This is an 8-clock field that is used to provide a 32-bit
(A31 - A0) memory address.
The AT49LH002 only decodes the last six MADDR nibbles (A23 - A0) and ignores address
bits A31 - A24 and A22 - A18. Address bit A23 is used to determine whether reads or writes to
the device will be directed to the memory array (A23 = 1) or to the register space (A23 = 0).
Addresses are transferred to the device with the most significant nibble first.
FWH4/LFRAME
FWH/LAD[3:0]
FWH/LAD[3:0]
010xb
011xb
CLK
Cycle Type
LPC Memory Read
LPC Memory Write
START
CYCTYPE
+ DIR
MADDR MADDR MADDR
MADDR
MADDR MADDR MADDR MADDR
AT49LH002
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