AT49LW080-33JC SL383 Atmel, AT49LW080-33JC SL383 Datasheet
AT49LW080-33JC SL383
Specifications of AT49LW080-33JC SL383
Related parts for AT49LW080-33JC SL383
AT49LW080-33JC SL383 Summary of contents
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... Green (Pb/Halide-free) Packaging Option 1. Description The AT49LW080 is a Flash memory device designed to be compatible with the Intel 82802AC and the Intel 82802AB Firmware Hub (FWH) devices for PC-Bios Applica- tion. A feature of the AT49LW080 is the nonvolatile memory core. The high- performance memory is arranged in sixteen 64-Kbyte sectors (see ...
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... Note that, while current for 12V programming will be drawn from V from the same supply as V from either pin. 2. Pin Configurations 2.1 32-lead PLCC Top View 2.2 32-lead TSOP Top View AT49LW080 2 ≤ Internal V detection circuitry automatically configures the PP PPLK PP , 3.3V programming board solutions should design such that V ...
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... FWH features, security features and registers are unavailable. A row/column (R/C) pin deter- mines which set of addresses “rows or columns” are latched. 3. Block Diagram 1966G–FLASH–3/05 WP TBL FGPI (4:0) FWH ID (3:0) INTERFACE FWH (4:0) CLK INIT OE R/C WE A/A MUX RY/BY INTERFACE A10 - A0 I/O7 - I/O0 AT49LW080 FLASH ARRAY CONTROL LOGIC RST IC 3 ...
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... ID[3:0] INPUT X FGPI[4:0] INPUT X TBL INPUT X AT49LW080 4 details the usage of each of the device pins. Most of the pins have dual functionality, + 0.3V max, unless otherwise noted. CC Interface A/A Mux Name and Function INTERFACE CONFIGURATION PIN: This pin determines which interface is operational. This pin is held high to enable the A/A Mux interface. This pin is held low to enable the FWH interface ...
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... No connects appear only on the 40-lead TSOP package READY/BUSY: Valid only in A/A Mux Mode. This output pin is a reflection of bit 7 in the X status register. This pin is used to determine sector erase or program completion. AT49LW080 ≤ 3.3V or 12V. With V , memory contents cannot PPLK ...
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... Likewise, the device has a wake time (t INIT high until writes to the CUI are recognized. A reset latency will occur if a reset procedure is performed during a programming or erase operation. AT49LW080 6 lists the seven required signals used for the FWH interface. ...
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... FWH memory may be providing status information instead of memory array data). 5.4 Cycle Types There are two types of cycles that are supported by the AT49LW080: FWH Memory Read and FWH Memory Write. FWH Memory Read or Write cycles start with a preamble. 5.4.1 Preamble The preamble consists of a START, IDSEL, 28-bit Address and MSIZE fields ...
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... Once SYNC is achieved, the device then returns the data in two clocks and gives ownership of the bus back to the master with a TAR phase. AT49LW080 8 Table 6-2. TAR and SYNC fields are described below. Commands using the read shows a device that requires three SYNC clocks to access data ...
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... Figure 6-1. FWH Single-byte Read Waveforms CLK FWH4 FWH[3:0] START IDSEL 1966G–FLASH–3/05 Table 6-1. Valid SYNC Values Indication Ready: SYNC achieved with no error. Short Wait: Part indicating wait states. MADDR MSIZE TAR SYNC(3) PREAMBLE AT49LW080 DATA TAR 9 ...
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... MADDR 10 MSIZE 11 TAR0 12 TAR1 WSYNC 15 RSYNC 16 DATA 17 DATA 18 TAR0 19 TAR1 Note: 1. Field contents are valid on the rising edge of the present clock cycle. AT49LW080 10 (1) Field Contents FWH[3:0] FWH[3:0] Direction 1101b IN 0000b to IN 1111b YYYY IN 0000b (1 byte 1111b then Float 1111b (float) ...
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... Flash command. OUT The FWH Flash memory drives FWH0 - FWH 3 to 1111b to indicate a 1111b then Float turnaround cycle. Float then The FWH Flash memory floats its outputs, the master (ICH) takes control IN of FWH3 - FWH0. AT49LW080 TAR SYNC TAR Figure 6-2 and 11 ...
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... TBL or WP during a program or erase operation may cause unpredictable results. If the state of TBL or WP changes during a program suspend or erase suspend state, the changes to the device’s locking status do not take place immediately. The suspended operation AT49LW080 12 , during the bus operation; the memory will tri-state ...
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... Sector-locking Registers The AT49LW080 has 16 (LR0 - LR15) sector-locking registers. Each sector-locking register con- trols the lock protection for 64K bytes of memory as shown in registers are accessible through the register memory address shown in the third column of 6-5. The sector-locking registers are read/write as shown in the last column of sector has three dedicated locking bits as shown in 1966G– ...
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... Table 6-5. Sector-locking Registers for AT49LW080 Register Name Sector Size LR0 64K LR1 64K LR2 64K LR3 64K LR4 64K LR5 64K LR6 64K LR7 64K LR8 64K LR9 64K LR10 64K LR11 64K LR12 64K LR13 64K LR14 64K LR15 ...
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... Lock-down, Write Lock, Data 1 Data AT49LW080 (1) Resulting Sector State Full access Write locked. Default state at power-up Locked open (full access locked down) Write locked down Read locked Read and write locked Read locked down Read and write locked down 15 ...
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... Reads status of general-purpose input pin (PLCC-30/TSOP-7) FGPI[3] 3 Reads status of general-purpose input pin (PLCC-3/TSOP-15) FGPI[2] 2 Reads status of general-purpose input pin (PLCC-4/TSOP-16) FGPI[1] 1 Reads status of general-purpose input pin (PLCC-5/TSOP-17) FGPI[0] 0 Reads status of general-purpose input pin (PLCC-6/TSOP-18) AT49LW080 16 Table 6- recommended that 1966G–FLASH–3/05 ...
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... Write Addr Write 1 XXXX Write Write 1 XXXX Write 2 Write XXXX 2 Write XXXX 1 Write XXXX voltage. PP Identifier Codes Address (AID) 000000 000001 AT49LW080 2nd Bus Cycle Data Operation Addr FF 20 Write Write Addr B0 D0 (6) 90 Read AID 70 Read XXXX 50 page Table 7-1. ...
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... Before a byte can be programmed, it must be erased. The erased state of the memory bits is a logical “1”. Since the AT49LW080 does not offer a complete chip erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. Successful sector erase requires that the corresponding sector’ ...
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... Error flags in the status register can only be set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions. The Clear Status Register command functions independently of the applied V 1966G–FLASH–3/05 AT49LW080 must remain at V (the same V PP PPH1/2 voltage ...
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... Lock bit, TBL pin or WP pin only after a sector erase or program operation. Depending on the attempted operation, it informs the system whether or not the selected sector is locked reserved for future use and should be masked out when polling the status register. AT49LW080 20 1 Ready ...
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... A/A Mux Mode are provided on pages starting from The AT49LW080 is designed to offer a parallel programming mode for faster factory program- ming. This mode, called A/A Mux Mode, is selected by having this IC pin high. The IC pin is pulled down internally in the AT49LW080 modest current should be expected to be drawn (see Table 4-1 on page 4 the component: R/C, OE, WE, and RST ...
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... Inputs are not “5-volt safe.” may be changed on IC and ID pins (up to 200 µA) if pulled against internal pull-downs. Refer to the pin descriptions not violate processor or chipset specifications regarding the INIT pin voltage. AT49LW080 22 *NOTICE: (1)(2)(4) (1)(2)(3) may overshoot to +13.0V for periods <20 ns. ...
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... No internal operations in progress CLK MHz (2) Any internal operation in progress OUT ≥ 3 11.4 - 12.6V PP per the PCI output V and V spec Memory Core + I FWH Interface AT49LW080 Min 3.0 11.4 1.5 1.5 ( 100 (3) IL (3) Max, (2) (2) Max Units 3 (4) µ 200 µ ...
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... Notes: 1. PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than16 MHz may be guaranteed by design rather than testing. 2. Applies only to rising edge of signal. 14.2 Clock Waveform AT49LW080 24 Condition ≤ 0 < V OUT CC 0.3 V < V <0 OUT CC 0 ...
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... Input Hold Time Reset Active Time after Power Stable Reset Active Time after CLK Stable (2) Reset Active to Output Float Delay CLK V TEST t VAL FWH[3:0] (Valid Output Data) FWH[3:0] (Float Output Data) t OFF CLK t SU Inputs Valid AT49LW080 Min 100 TEST ...
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... AC Waveform for Reset Operation V IH RST V IL 21. Sector Programming Times Parameter (2) Byte Program Time (2) Sector Program Time (2) Sector Erase Time Notes: 1. Typical values measured Excludes system-level overhead. AT49LW080 26 of overdrive over this CC t PLPH 3. (1) Typ Max 30.0 300 2.0 20 ...
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... Product ID are PP PPLK Conditions max GND out min -2 min -100 µ min this specification is not CC (1)(2) t PLRH t PLPH AT49LW080 on V enables PPH1/2 PP Min Max Unit 0 0 -0.5 0.8 +10 µA 0.85 V min 0 Min Max Unit 100 ns 20 µ ...
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... A/A Mux Read Timing Diagram V IH ADDRESSES AVCL PHAV RST V IL AT49LW080 28 (1)(2) (2) ( after the rising edge of R/C without impact on t CHQV GLQV . CC t AVAV Row Address Column Address Stable Stable t t CLAX AVCH t CHAX t CHQV High-Z t GLQX Min Max 250 ...
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... Hold from Valid SRD, RY/BY High QVVL PP1,2 Notes: 1. Refer to “A/A Mux Read-only Operations” for valid 0°C to +85°C, 3.3V ± 0. 1966G–FLASH–3/05 (1)(2) (1) (1) (1) (1) (1) (1) and AT49LW080 Min Max 1 100 100 50 100 150 0 0 for sector erase or program, or other commands. Units µs ns ...
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... V IH RST PPH1 NOTES power-up and standby Write sector erase or program setup C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command AT49LW080 AVCH t CLAX t t PHWL WHWL t WLWH t WHDX t DVWH ...
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... Plastic J-leaded Chip Carrier Package (PLCC) 40T 40-lead, Thin Small Outline Package (TSOP) 1966G–FLASH–3/05 Ordering Code AT49LW080-33JC AT49LW080-33TC Ordering Code AT49LW080-33JX Package Type AT49LW080 Package Operation Range 32J Extended Commercial 40T (0° to 85°C) Package Operation Range Extended Commercial 32J (0° ...
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... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT49LW080 32 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...
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... Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 1966G–FLASH–3/05 PIN SEATING PLANE A1 TITLE 40T, 40-lead ( Package) Plastic Thin Small Outline Package, Type I (TSOP) AT49LW080 0º ~ 8º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – ...
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