AT49LW080-33JC SL383 Atmel, AT49LW080-33JC SL383 Datasheet - Page 10

• Manufacturer Part Number: AT49LW080-33JC SL383
• Description: IC FLASH 8MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LW080-33JC SL383

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6-2.
Note:
10
Clock Cycle
13 - 14
3 - 9
10
11
12
15
16
17
18
19
1
2
1. Field contents are valid on the rising edge of the present clock cycle.
AT49LW080
FWH Read Cycle
Field Name
MADDR
WSYNC
RSYNC
START
MSIZE
IDSEL
TAR0
TAR1
TAR0
TAR1
DATA
DATA
Field Contents
0000b (READY)
0000b (1 byte)
0101b (WAIT)
1111b (float)
1111b (float)
FWH[3:0]
1101b
0000b
1111b
1111b
1111b
YYYY
YYYY
YYYY
to
(1)
Float then OUT
FWH[3:0]
then Float
then Float
Float then
Direction
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
Comments
FWH4 must be active (low) for the part to respond.
Only the last start field (before FWH4 transitioning
high) should be recognized. The START field contents
indicate an FWH memory read cycle.
Indicates which FWH device should respond. If the
IDSEL (ID select) field matches the value ID[3:0],
then that particular device will respond to subsequent
commands.
These seven clock cycles make up the 28-bit memory
address. YYYY is one nibble of the entire address.
Addresses are transferred most significant nibble first.
The FWH will only support single-byte transfers.
In this clock cycle, the master (ICH) has driven the
bus to all 1s and then floats the bus, prior to the next
clock cycle. This is the first part of the bus “turnaround
cycle”.
The FWH takes control of the bus during this cycle.
During the next clock cycle, it will be driving “sync
data”.
The FWH outputs the value 0101, a wait-sync
(WSYNC, a.k.a. “short-sync”), for two clock cycles.
This value indicates to the master (ICH) that data is
not yet available from the part. This number of wait-
syncs is a function of the device’s access time.
During this clock cycle, the FWH will generate a
“ready-sync” (RSYNC) indicating that the least
significant nibble of the least significant byte will be
available during the next clock cycle.
YYYY is the least significant nibble of the least
significant data byte.
YYYY is the most significant nibble of the least
significant data byte.
The FWH Flash memory drives FWH0 - FWH3 to
1111b to indicate a turnaround cycle.
The FWH Flash memory floats its outputs, the master
(ICH) takes control of FWH3 - FWH0.
1966G–FLASH–3/05