AT49LW080-33JC SL383 Atmel, AT49LW080-33JC SL383 Datasheet - Page 11

• Manufacturer Part Number: AT49LW080-33JC SL383
• Description: IC FLASH 8MBIT 33MHZ 32PLCC
• Manufacturer: Atmel

Specifications of AT49LW080-33JC SL383

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 33MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 32-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.2
6.2.1
Figure 6-2.
Table 6-3.
Note:
1966G–FLASH–3/05
Clock Cycle
3 - 9
10
11
12
13
14
15
16
17
FWH[3:0]
1
2
Write
1. Field contents are valid on the rising edge of the present clock cycle.
FWH4
Write Cycles, Single Byte
CLK
FWH Single-byte Write Waveforms
FWH Write Cycle
Field Name
MADDR
RSYNC
START
MSIZE
IDSEL
DATA
DATA
TAR0
TAR1
TAR0
TAR1
START
IDSEL
Write operations consist of preamble, data, TAR and SYNC fields as shown in
described in
All devices that support FWH Memory Write cycles must support single-byte writes. FWH Mem-
ory Write cycles use the same preamble as FWH Memory Read cycles.
For write cycles, after the preamble, the master writes the low nibble, then the high nibble of
data. After that the master drives a TAR field to give ownership of the bus to the FWH. After the
second clock of the TAR phase, the target device assumes the bus and begins driving SYNC
values. A TAR field to give control back to the master follows this.
Field Contents
0000b (1 byte)
1111b (float)
1111b (float)
FWH[3:0]
0000b to
1110b
1111b
YYYY
YYYY
YYYY
1111b
0000b
1111b
PREAMBLE
MADDR
Table
(1)
6-3.
FWH[3:0]
Direction
Float then
then Float
Float then
then float
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
MSIZE
DATA
Comments
FWH4 must be active (low) for the part to respond. Only the last start field
(before FWH4 transitioning high) should be recognized. The START field
contents indicate an FWH memory write cycle.
Indicates which FWH device should respond. If the IDSEL (ID select) field
matches the value ID[3:0], then that particular device will respond to
subsequent commands.
These seven clock cycles make up the 28-bit memory address. YYYY is
one nibble of the entire address. Addresses are transferred most
significant nibble first.
The FWH only supports single-byte writes.
This field is the least significant nibble of the data byte. This data is either
the data to be programmed into the Flash memory or any valid Flash
command.
This field is the most significant nibble of the data byte.
In this clock cycle, the master (ICH) has driven the bus to all 1s and then
floats the bus prior to the next clock cycle. This is the first part of the bus
“turnaround cycle”.
The FWH takes control of the bus during this cycle. During the next clock
cycle it will be driving the “sync” data.
The FWH outputs the values 0000, indicating that it has received data or
a Flash command.
The FWH Flash memory drives FWH0 - FWH 3 to 1111b to indicate a
turnaround cycle.
The FWH Flash memory floats its outputs, the master (ICH) takes control
of FWH3 - FWH0.
TAR
SYNC
TAR
AT49LW080
Figure 6-2
and
11