MT46H8M32LFB5-10 IT:A TR Micron Technology Inc, MT46H8M32LFB5-10 IT:A TR Datasheet
MT46H8M32LFB5-10 IT:A TR
Specifications of MT46H8M32LFB5-10 IT:A TR
Related parts for MT46H8M32LFB5-10 IT:A TR
MT46H8M32LFB5-10 IT:A TR Summary of contents
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Mobile DDR SDRAM MT46H16M16LF – 4 Meg banks MT46H8M32LF/LG – 2 Meg banks For the latest data sheet, refer to Micron’s Web site: www.micron.com Features • 1.70–1.95V DD/ ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 256Mb Mobile DDR Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the Mobile DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes: one for the lower byte and one for the upper byte ...
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... An auto refresh mode is provided, along with a power-saving power-down mode. Deep power-down mode is offered to achieve maximum power reduction by eliminating the power draw of the memory array. Data will not be retained when the device enters DPD mode. Self refresh mode offers temperature compensation through an on-chip temperature sensor and partial-array self refresh, which enables users to achieve additional power savings ...
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... PDF: 09005aef82091978 / Source: 09005aef8209195b MT46H16M16LF__2.fm - Rev. H 6/08 EN Bank 3 Bank 2 Bank 1 13 Bank 0 Row- 13 Row- Bank 0 MUX address Memory 8,192 Latch array and (8,192 x 256 x 32) decoder Sense amplifiers 16,384 I/O gating DM mask logic Bank control logic 256 (x32) Column ...
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... JEDEC-standard x32 DQ configuration shown. PDF: 09005aef82091978 / Source: 09005aef8209195b MT46H16M16LF__2.fm - Rev. H 6/08 EN Bank 3 Bank 2 Bank 1 13 Bank 0 Row- 12 Row- Bank 0 address MUX Memory 8,192 Latch array and (4,096 x 256 x 64) decoder Sense amplifiers 4,092 I/O gating DM mask logic Bank control logic 256 ...
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Ballouts and Ball Descriptions Figure 4: 60-Ball VFBGA Ball Assignments – 8mm x 9mm (Top View Notes test pin that must be connected to V PDF: ...
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Figure 5: 90-Ball VFBGA Ball Assignments – 8mm x 13mm (Top View Notes test pin that must be connected to V ...
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... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. During a PRECHARGE command, A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
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... Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ or WRITE commands, to select one location out of the memory array in the respective bank. During a PRECHARGE command, A10 determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH) ...
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Table 4: 90-Ball VFBGA Ball Description (Continued) Ball Numbers Symbol V Q A3, B9, C1, E1, L1, M9, SS N1, P9, R3 A9, F1 A1 TEST D9 PDF: 09005aef82091978 / ...
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... Functional Description The 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits internally configured as a quad-bank DRAM. Each of the 67,108,864-bit banks on the x16 is organized as 8,192 rows by 512 columns by 16 bits. Each of the 67,108,864-bit banks on the x32 is organized as 4,096 rows by 512 columns by 32 bits for the standard addressing configuration ...
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... BA1 = 0) and will retain the stored information until it is programmed again, the device goes into deep power-down mode, or the device loses power. Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait before initiating the subsequent operation ...
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CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first output data. The latency can be set to two or three clocks, as shown in Figure ...
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Table 5: Burst Definition Table Burst Length Starting Column Address PDF: 09005aef82091978 / Source: 09005aef8209195b MT46H16M16LF__2.fm - Rev. H 6/08 EN 256Mb: x16, x32 Mobile DDR SDRAM Order ...
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Figure 7: CAS Latency CK# Command DQS CK# Command DQS Notes the cases shown. 2. Shown with nominal PDF: 09005aef82091978 / Source: 09005aef8209195b MT46H16M16LF__2.fm - Rev T1n CK READ NOP ...
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... Partial-Array Self Refresh For further power savings during SELF REFRESH, the partial-array self refresh (PASR) feature enables the controller to select the amount of memory that will be refreshed during SELF REFRESH. Table 6: Partial-Array Self Refresh Options ...
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Figure 8: Extended Mode Register BA1 BA0 A12 E14 E13 E12 E14 E13 Mode Register Definition 0 0 Standard mode register 0 1 Reserved 1 0 Extended mode register 1 1 Reserved E12 E11 E10 ...
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CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration of the clock stop mode. One clock cycle and at least one NOP or DESELECT is required after the clock is restarted before ...
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Commands Tables 7 and 8 provide a quick reference of available commands. This is followed by a description of each command. Three additional truth tables provide CKE commands and current/next state information (see Table 9 on page 51, Table 10 ...
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... Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location ...
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PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( of concurrent auto precharge, ...
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... Deep Power-Down Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power draw of the memory array. Data will not be retained when the device enters deep power-down mode. Figure 10: Mobile DRAM State Diagram ...
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Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank ...
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Figure 12: Example: Meeting T0 T1 CK# CK Command ACT NOP A0–A12 Row BA0, BA1 Bank x READs READ burst operations are initiated with a READ command, as shown in Figure 13 on page 28. The starting column and bank ...
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Figure 13: READ Command A9, A11, A12 Notes column address bank address enable auto precharge 4. DIS AP = disable auto precharge 5. x16 DQ configuration example PDF: 09005aef82091978 / ...
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Figure 14: READ Burst T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Commmand READ Bank a, Address Col n DQS DQ Notes OUT Shown with nominal ...
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Figure 15: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if 4, the ...
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Figure 16: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT ...
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Figure 17: Random READ Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if 4 ...
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Truncated READs Data from any non-auto precharge READ burst may be truncated with a BURST TERMI- NATE command, as shown in Figure 18. The BURST TERMINATE latency is equal to the READ (CAS) latency; for example, the BURST TERMINATE command ...
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CKE = HIGH. Figure 19: READ-to-WRITE T0 CK# CK Command READ Bank, Address Col n DQS CK# CK Command READ Bank, Address Col n DQS DQ DM Notes OUT ...
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Figure 20: READ-to-PRECHARGE T0 CK Command READ Bank a, Address Col n DQS Command READ Bank a , Address Col n DQS DQ Notes OUT ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 21 on page 37. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...
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Figure 21: WRITE Command CK# CKE CS# RAS# CAS# WE# A0–A9 A11, A12 A10 BA0, BA1 Notes column address bank address enable auto precharge. 4. DIS AP = disable auto ...
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Figure 22: WRITE Burst Notes uninterrupted burst shown. 3. A10 is LOW with the WRITE command (auto precharge is disabled). PDF: 09005aef82091978 / Source: 09005aef8209195b MT46H16M16LF__2.fm - Rev ...
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Figure 23: Consecutive WRITE-to-WRITE T0 CK# CK Command WRITE Bank, Address Col b t DQSS (NOM) DQS DQ DM Notes uninterrupted burst shown. 3. Each WRITE command may be to any bank. ...
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Figure 25: Random WRITE Cycles T0 CK# CK Command WRITE Bank, Address Col b t DQSS (NOM) DQS DQ DM Notes (or x', n', a', g') = the next data-in following D grammed burst order. ...
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Figure 26: WRITE-to-READ – Uninterrupting T0 CK# CK Command WRITE NOP Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) t DQSS DQS DQSS (MAX) t DQSS ...
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Figure 27: WRITE-to-READ – Interrupting T0 CK# CK Command WRITE NOP Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 28: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS (NOM) t DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) ...
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Figure 29: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK Command WRITE NOP Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 30: WRITE-to-PRECHARGE – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS ...
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Figure 31: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK Command WRITE NOP Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS ...
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PRECHARGE The PRECHARGE command (Figure 32) is used to deactivate the open row in a partic- ular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( A10 ...
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Power-Down Power-down (Figure 42 on page 70) is entered when CKE is registered LOW. If power- down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active ...
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... Deep Power-Down (DPD) Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power of the memory array. Data will not be retained when the device enters deep power-down mode. Before entering DPD mode, the DRAM must be in all banks idle state with no activity on the data bus ( with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW ...
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Figure 35: Deep Power-Down T0 CK# CK CKE Cdommand NOP All banks idle with no activity on the data bus Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPD = deep power-down command. 3. Upon exit ...
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Table 9: Truth Table – CKE Notes 1–5 apply to all commands in this table CKE CKE Current State Active power-down L L Deep power-down L L (Precharge) power-down L L SELF REFRESH L ...
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Table 10: Truth Table – Current State Bank n – Command to Bank n Notes 1–6 apply to all states listed in this table; notes appear below and on next page Current State CS# RAS# Any ...
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LECT or NOP commands must be applied on each positive clock edge during these states. Refreshing Accessing mode register all: 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks be ...
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Table 11: Truth Table – Current State Bank n – Command to Bank m Notes 1–6 apply to all states listed in this table; the other referenced notes appear below and on next page Current State CS# RAS# Any H ...
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This device supports concurrent auto precharge such that when a read with auto precharge is enabled or a write with auto precharge is enabled, any command to other banks is sup- ported, as long as that command does not interrupt ...
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Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in Table 12 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those ...
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Table 14: Capacitance (x16, x32) Note 41 on page 65 applies to all parameters in this table; notes appear on pages 63–65 Parameter Delta input/output capacitance: DQ, DQS, DM Delta input capacitance: command and address Delta input capacitance: CK, CK# ...
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Table 15: I Specifications and Conditions (x16) DD Notes: 1– apply to all parameters in this table; notes appear on pages 63–65; V Parameter/Condition Operating one bank active-precharge current (MIN); CKE = HIGH; ...
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Table 16: I Specifications and Conditions (x32) DD Notes: 1– apply to all parameters in this table; notes appear on pages 63–65; V Parameter/Condition Operating one bank active-precharge current RFC = RFC (MIN); CK ...
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Table 17 Specifications and Conditions (x16, x32) DD Notes: 1–5, 9, 10, 36, and 39 apply to all parameters in this table; notes appear on pages 63–65 1.70–1.95V DD DD Parameter/Condition Self refresh current: ...
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Table 18: Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–6, 22 apply to all parameters in this table; notes appear on pages 63–65; V Parameter Access window of DQ from CK/CK# CK high-level width CK low-level width Clock cycle ...
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Table 18: Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–6, 22 apply to all parameters in this table; notes appear on pages 63–65; V Parameter DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b ...
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Notes 1. All voltages referenced All parameters assume proper device initialization. 3. Tests for AC timing nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ...
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MIN ( the minimum absolute value for the respective parameter. 17. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 18. The data valid window is derived ...
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Reduced page-size option (A12). See page 1. 36. Current may be slightly higher for up to 500ms when entering this operating mode. 37. The maximum 38. Deep power-down current is nominal value at 25°C. The parameter is not tested. ...
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Timing Diagrams Figure 37: Data Output Timing – LDQS DQ (Last data valid (First data no longer valid ...
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Figure 38: Data Output Timing – T1 CK# CK DQM0/DQM1/DQM2/DQM3 DQ (Last data valid (First data no longer valid (Last data valid ...
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Figure 39: Data Output Timing – T0 CK# CK Command READ 1 DQS or LDQS/UDQS 2 All DQ values, collectively Notes transitioning after DQS transition define 2. All DQ must transition the DQ ...
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Figure 41: Initialize and Load Mode Registers ( ( ) ) CK LVCMOS High level ( ( ) ) CKE ( ( ...
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Figure 42: Power-Down Mode (Active or Precharge CKE Command 1 VALID Address VALID DQS DQ DM power-down Notes this ...
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Figure 43: Auto Refresh Mode CKE Command NOP 2 PRE A0–A9, A11, A12 1 All banks 1 A10 One bank BA0, BA1 ...
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Figure 44: Self Refresh Mode T0 CK CKE Command NOP Address DQS Notes: 1. Clock must be stable, cycling within specifications ...
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Figure 45: Bank Read – Without Auto Precharge CKE Command 6 ACT NOP A0– A11–Ai A10 ...
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Refer to Figures 37 and 38 on pages 66–67 for DQS and DQ timing details. Figure 46: Bank Read – with Auto Precharge CKE ...
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Refer to Figures 37 and 38 on pages 66–67 for DQS and DQ timing details. Figure 47: Bank Write – Without Auto Precharge CKE ...
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Figure 48: Bank Write – with Auto Precharge CKE Command NOP ACT A0–A9 RA A11, A12 A10 RA t ...
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Figure 49: Write – DM Operation CKE NOP 6 Command ACT A0–A9 A11, A12 RA A10 ...
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Package Dimensions Figure 50: 60-Ball VFBGA Package Seating plane A 0.1 A 60x Ø0.45 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.6 7.2 0.8 TYP 0.8 TYP Note: ...
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Figure 51: 90-Ball VFBGA Package Seating plane A 0 ±0.1 90X 0.45 Dimensions apply to solder balls post- reflow. Pre-reflow balls are Ø0. Ø0.4 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 Note: All ...