MT46H8M32LFB5-10 IT:A TR Micron Technology Inc, MT46H8M32LFB5-10 IT:A TR Datasheet - Page 59

• Manufacturer Part Number: MT46H8M32LFB5-10 IT:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M32LFB5-10 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 16:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
HIGH between valid commands; Address inputs are
switching every two clock cycles; Data bus inputs
are stable
Precharge power-down standby current: All banks idle; CKE is LOW;
CS is HIGH,
Data bus inputs are stable
Precharge power-down standby current with clock stopped: All
banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Precharge non-power-down standby current: All banks idle; CKE =
HIGH; CS = HIGH;
switching; Data bus inputs are stable
Precharge non-power-down standby current with clock stopped:
All banks idle; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH;
Data bus inputs are stable
Active power-down standby current with clock stopped: One
bank active; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Active non-power-down standby current: One bank active; CKE =
HIGH; CS = HIGH;
switching; Data bus inputs are stable
Active non-power-down standby current with clock stopped: One
bank active; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Operating burst read: One bank active; BL = 4; CL = 3;
I
percent data changing each burst
Operating burst WRITE: One bank active; BL = 4;
t
percent data changing each burst
Auto refresh current: Burst refresh; CKE = HIGH;
Address and control inputs are switching; Data bus
inputs are stable
Deep power-down current: Address and control inputs are stable;
Data bus inputs are stable
OUT
RFC =
CK =
= 0mA; Address inputs are switching every two clock cycles; 50
t
t
CK (MIN); Address inputs are switching; 50
RFC (MIN);
t
t
CK =
CK =
I
Notes: 1–5, 9, 11 apply to all parameters in this table; notes appear on pages 63–65; V
DD
t
t
t
t
CK (MIN); Address and control inputs are switching;
Specifications and Conditions (x32)
CK (MIN); Address and control inputs are switching;
t
CK =
CK =
CK =
t
t
t
CK (MIN); Address and control inputs are
CK (MIN); Address and control inputs are
CK (MIN); CKE = HIGH; CS =
JEDEC-standard
option
Reduced page-size
option
JEDEC-standard
option
Reduced page-size
option
t
t
RC
RC =
t
CK =
=
t
t
RFC (MIN)
REFI
59
t
CK (MIN);
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
Standard
Standard
Symbol
power
power
I
I
I
I
I
I
I
I
I
I
I
I
DD
I
DD
I
DD
DD
DD
DD
DD
Low
Low
I
I
DD
DD
DD
I
DD
I
DD
DD
DD
DD
DD
DD
DD
2NS
3NS
2PS
2PS
3PS
4W
4W
2N
3N
5
2P
2P
3P
4R
0
0
5
8
a
300
220
300
220
135
160
140
80
70
25
25
10
65
10
-6
5
5
3
3
Electrical Specifications
Max
©2005 Micron Technology, Inc. All rights reserved.
300
220
300
220
115
140
120
-75
65
55
20
20
10
60
10
5
5
3
3
DD
/V
DD
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Q = 1.70–1.95V
µA
µA
µA
Notes
16, 36
16, 35
16, 36
16, 35
36, 38
36
36
36
36
16
16
16
20