MT46H8M32LFB5-10 IT:A TR Micron Technology Inc, MT46H8M32LFB5-10 IT:A TR Datasheet - Page 24

• Manufacturer Part Number: MT46H8M32LFB5-10 IT:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M32LFB5-10 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PRECHARGE
BURST TERMINATE
AUTO REFRESH
SELF REFRESH
Auto Precharge
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (
of concurrent auto precharge, where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in the current bank and does
not violate any other timing parameters. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” After a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state) or if the previously open row is
already in the process of precharging.
The BURST TERMINATE command is used to truncate READ bursts (with auto
precharge disabled). The most recently registered READ command prior to the BURST
TERMINATE command will be truncated, as described in “Operations” on page 26. The
open page from which the READ burst was terminated remains open.
The AUTO REFRESH command is nonpersistent and must be issued each time a refresh
is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 256Mb Mobile DDR
SDRAM requires AUTO REFRESH cycles at an average interval of 7.8125µs (MAX).
To enable improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided.
Although not a JEDEC requirement, CKE must be active (HIGH) during the auto refresh
period to provide for future functionality features. The auto refresh period begins when
the AUTO REFRESH command is registered, and it ends
The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM,
even if the rest of the system is powered down. When in the self refresh mode, the
Mobile DDR SDRAM retains data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command, except that CKE is disabled
(LOW). All command and address input signals except CKE are “Don’t Care” during
SELF REFRESH. For details on entering and exiting self refresh mode, see Figure 44 on
page 72. During SELF REFRESH, the device is refreshed as identified in the extended
mode register (see PASR setting).
Auto precharge is a feature that performs the same individual-bank PRECHARGE func-
tion described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
t
RP) after the PRECHARGE command is issued. The exception is the case
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t
RFC later.
©2005 Micron Technology, Inc. All rights reserved.
Commands