MT46H8M32LFB5-10 IT:A TR Micron Technology Inc, MT46H8M32LFB5-10 IT:A TR Datasheet - Page 61

• Manufacturer Part Number: MT46H8M32LFB5-10 IT:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M32LFB5-10 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 18:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Parameter
Access window of DQ from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
Minimum
Auto precharge write recovery + precharge time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input HIGH pulse width
DQS input LOW pulse width
DQS–DQ skew, DQS to last DQ valid, per group, per
access
WRITE command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Data valid output window (DVW)
Half clock period
Data-out High-Z window from CK/CK#
Data-out Low-Z window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE or ACTIVE-to-AUTO REFRESH
command period
ACTIVE-to-READ or WRITE delay
Refresh period
Average periodic refresh interval
Average periodic refresh interval (x32)
AUTO REFRESH command period
PRECHARGE command period
t
CKE HIGH/LOW time
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 1–6, 22 apply to all parameters in this table; notes appear on pages 63–65; V
(x16)
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
t
t
DQSCK(3)
DQSCK(2)
Symbol
61
t
t
t
t
t
t
t
t
t
t
t
DQSQ
t
DQSH
AC(3)
AC(2)
DIPW
t
t
t
t
t
CK(3)
CK(2)
t
t
DQSL
DQSS
HZ(3)
HZ(2)
t
t
t
MRD
t
t
t
t
t
t
t
DAL
DSH
t
QHS
RCD
REFI
REFI
CKE
t
n/a
t
t
IPW
RAS
t
t
t
DSS
t
REF
RFC
QH
DH
IH
IH
CH
HP
CL
DS
IS
IS
RC
RP
LZ
F
S
F
S
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
-
Min
0.45
0.35
0.75
t
0.45
0.35
t
t
t
2.0
2.0
0.5
0.5
1.8
2.0
2.0
0.2
0.2
QH -
CH,
t
1.0
1.1
1.1
1.2
1.2
2.6
12
QHS
42
60
18
70
18
HP
CL
6
1
2
–
–
–
–
–
–
–
-6
t
DQSQ
70,000
Max
0.55
0.55
1.25
0.65
15.6
5.0
6.5
5.0
6.5
0.6
0.6
0.5
5.0
6.5
7.8
64
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
-
Electrical Specifications
Min
0.45
0.45
0.75
0.75
0.75
t
t
22.5
22.5
t
t
2.0
2.0
7.5
1.8
2.0
2.0
0.4
0.4
0.2
0.2
QH -
t
1.0
1.3
1.3
1.5
1.5
2.6
CH,
12
QHS
45
75
70
HP
CL
1
2
–
–
–
–
–
–
–
–
-75
©2005 Micron Technology, Inc. All rights reserved.
t
DQSQ
70,000
DD
Max
0.55
0.55
1.25
0.75
15.6
6.0
6.5
6.0
6.5
0.6
0.6
0.6
6.0
6.5
7.8
64
/V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DD
Q = 1.70–1.95V
Units
t
t
t
t
t
t
t
t
t
ms
ns
CK
CK
ns
CK
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
ns
ns
ns
ns
ns
µs
µs
ns
ns
19,23,31
19,23,31
Notes
18, 19
12, 30
12, 30
18, 19
24
32
33
18
24
11
11
11
11
33
25
37
37