MT46H8M32LFB5-10 IT:A TR Micron Technology Inc, MT46H8M32LFB5-10 IT:A TR Datasheet - Page 14

• Manufacturer Part Number: MT46H8M32LFB5-10 IT:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M32LFB5-10 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
Initialization
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
1. The core power (V
2. After power supply voltages are stable and the CKE has been driven HIGH, it is safe to
3. After the clock is stable, a 200µs (MIN) delay is required by the Mobile DDR SDRAM
4. Issue a PRECHARGE ALL command.
5. Issue a NOP or DESELECT command for at least
6. Issue an AUTO REFRESH command followed by a NOP or DESELECT command for
The 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access
memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.
Each of the 67,108,864-bit banks on the x16 is organized as 8,192 rows by 512 columns by
16 bits. Each of the 67,108,864-bit banks on the x32 is organized as 4,096 rows by 512
columns by 32 bits for the standard addressing configuration.
The 256Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high-
speed operation. The double data rate architecture is essentially a 2n-prefetch architec-
ture, with an interface designed to transfer two data words per clock cycle at the I/O
balls. Single read or write access for the 256Mb Mobile DDR SDRAM consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coin-
cident with the ACTIVE command are used to select the bank and row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
The DLL circuit that is typically used on standard DDR devices is not necessary on the
Mobile DDR SDRAM. It has been omitted to save power.
Prior to normal operation, the Mobile DDR SDRAM must be initialized. The following
sections provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Mobile DDR SDRAMs must be powered up and initialized in a predefined manner.
Operational procedures other than those specified may result in undefined operation.
If there is an interruption to the device power, the initialization routine must be
followed to ensure proper functionality of the Mobile DDR SDRAM. The clock stop
feature is not available until the device has been properly initialized.
To properly initialize the Mobile DDR SDRAM, this sequence must be followed:
recommended that V
never exceed V
apply the clock.
prior to applying an executable command. During this time, a NOP or DESELECT
command must be issued on the command bus.
at least
DESELECT command for at least
AUTO REFRESH commands must be issued.
t
RFC time. Issue a second AUTO REFRESH command followed by a NOP or
DD
. Assert and hold CKE HIGH.
DD
) and I/O power (V
DD
and V
14
DD
Q be from the same power source, or V
t
RFC time. As part of the initialization sequence, two
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
DD
Q) must be brought up simultaneously. It is
t
RP time.
Functional Description
©2005 Micron Technology, Inc. All rights reserved.
DD
Q must