MT46H8M32LFB5-10 IT:A TR Micron Technology Inc, MT46H8M32LFB5-10 IT:A TR Datasheet - Page 54

• Manufacturer Part Number: MT46H8M32LFB5-10 IT:A TR
• Description: IC DDR SDRAM 256MBIT 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT46H8M32LFB5-10 IT:A TR

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 11:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Current State
Any
Idle
Row
activating,active,
or precharging
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
Truth Table – Current State Bank n – Command to Bank m
Notes 1–6 apply to all states listed in this table; the other referenced notes appear below and on next page
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKE
2. This table describes alternate bank operation, except where noted (for example, the cur-
3. Current state definitions:
RAS#
X
H
X
H
H
H
H
H
H
H
H
H
H
the previous state was SELF REFRESH) or after
power-down) or 200µs if the previous state was deep power-down).
rent state is for bank n and the commands shown are those allowed to be issued to bank m,
assuming that bank m is in such a state that given command is allowable). Exceptions are
covered in the notes below.
3a. The READ with auto precharge enabled or WRITE with auto precharge enabled states
can each be broken into two parts: the access period and the precharge period. For read
with auto precharge, the precharge period is defined as if the same burst were executed
with auto precharge disabled and then followed with the earliest possible PRECHARGE
command that still accesses all of the data in the burst. For write with auto precharge, the
precharge period begins when
abled. The access period starts with registration of the command and ends where the pre-
charge period (or
L
L
L
L
L
L
L
L
L
L
Idle:
Write:
CAS#
Row active: A row in the bank has been activated, and
Read:
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
WE#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
t
RP) begins.
The bank has been precharged, and
bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Command (Action)
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
n - 1
54
t
was HIGH and CKE
WR ends, with
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t
XP has been met (if the previous state was
t
WR measured as if auto precharge were dis-
n
is HIGH and after
t
RP has been met.
t
RCD has been met. No data
©2005 Micron Technology, Inc. All rights reserved.
t
XSR has been met (if
Operations
Notes
7, 10
3a, 7
3a, 7
3a,7
3a,7
7, 9
7
7
7
7