CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet - Page 22

• Manufacturer Part Number: CY7C1354A-166BGC
• Description: IC SRAM 9MBIT 166MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1108

Switching Waveforms
Read Timing
Notes:
39. Q(A
40. CE
41. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
42. R/W is “Don’t Care” when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W
43. BWc and BWd apply to 256Kx36 device only.
BWa#, BWb#
ADDRESS
output data in the burst sequence of the base address A
by the state of the MODE input.
inverted to the CE signal. For example, when CE is LOW on this waveform, CE
signal when new address and control are loaded into the SRAM.
ADV/LD#
2
1
timing transitions are identical to the CE signal. For example, when CE is LOW on this waveform, CE
) represents the first output from the external address A
CKE#
R/W#
CLK
OE#
CE#
DQ
[39, 40, 41, 42, 43]
A
1
t
t
t
t
t
S
S
S
S
S
t
KQLZ
Pipeline Read
A
2
t
t
t
t
t
PRELIMINARY
H
H
H
Pipeline Read
H
H
Q(A
1
)
t
KQ
2
, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined
t
KC
1
. Q(A
Q(A
t
KL
2
)
2
) represents the first output from the external address A
22
t
KQX
Q(A
2
2
is HIGH.
+1)
t
KH
BURST PIPELINE READ
(CKE# HIGH, eliminates
current L-H clock edge)
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Q(A
2
+2)
2
is LOW. CE
2
timing transitions are identical but
2
; Q(A
Q(A
(Burst Wraps around
2
+3)
to initial state)
2
+1) represents the next
Q(A
2
)
t
KQHZ