CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet - Page 5

• Manufacturer Part Number: CY7C1354A-166BGC
• Description: IC SRAM 9MBIT 166MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1108

Pin Descriptions—256Kx36
82, 83, 99, 100
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 81,
TQFP Pins
256Kx36
98, 92
37,
36,
93,
94,
95,
96
87
88
89
97
86
85
31
5C, 6C, 4G, 2R,
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
6R, 3T, 4T, 5T
PBGA Pins
256Kx36
4E, 6B
4M
4N
5G
3G
4H
3R
4P
5L
3L
4K
2B
4F
4B
ADV/LD
MODE
Name
PRELIMINARY
BWa,
BWb,
BWc,
SA0,
SA1,
BWd
CKE
R/W
CLK
CE
CE
CE,
OE
SA
2
2
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Type
Input
5
Synchronous Address Inputs: The address register is trig-
gered by a combination of the rising edge of CLK, ADV/LD
LOW, CKE LOW and true chip enables. SA0 and SA1 are the
two least significant bits of the address field and set the internal
burst counter if burst cycle is initiated.
Synchronous Byte Write Enables: Each 9-bit byte has its own
active low byte write enable. On load write cycles (when R/W#
and ADV/LD are sampled LOW), the appropriate byte write
signal (BWx) must be valid. The byte write signal must also be
valid on each cycle of a burst write. Byte write signals are
ignored when R/W is sampled HIGH. The appropriate byte(s)
of data are written into the device two cycles later. BWa con-
trols DQa pins; BWb controls DQb pins; BWc controls DQc
pins; BWd controls DQd pins. BWx can all be tied LOW if al-
ways doing write to the entire 36-bit word.
Synchronous Clock Enable Input: When CKE is sampled
HIGH, all other synchronous inputs, including clock are ig-
nored and outputs remain unchanged. The effect of CKE sam-
pled HIGH on the device outputs is as if the LOW-to-HIGH
clock transition did not occur. For normal operation, CKE must
be sampled LOW at rising edge of clock.
Read Write: R/W signal is a synchronous input that identifies
whether the current loaded cycle and the subsequent burst
cycles initiated by ADV/LD is a Read or Write operation. The
data bus activity for the current cycle takes place two clock
cycles later.
Clock: This is the clock input to CY7C1354A/GVT71256ZC36.
Except for OE, ZZ and MODE, all timing references for the
device are made with respect to the rising edge of CLK.
Synchronous Active LOW Chip Enable: CE and CE
with CE
CE
LOW at the rising edge of clock, initiates a deselect cycle. The
data bus will be High-Z two clock cycles after chip deselect is
initiated.
Synchronous Active High Chip enable: CE
and CE
erwise is identical to CE and CE
Asynchronous Output Enable: OE must be LOW to read data.
When OE is HIGH, the I/O pins are in high-impedance state.
OE does not need to be actively controlled for read and write
cycles. In normal operation, OE can be tied LOW.
Advance/Load: ADV/LD is a synchronous input that is used to
load the internal registers with new address and control signals
when it is sampled LOW at the rising edge of clock with the
chip is selected. When ADV/LD is sampled HIGH, then the
internal burst counter is advanced for any burst that was in
progress. The external addresses and R/W are ignored when
ADV/LD is sampled HIGH.
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst
sequence is selected. MODE is a static DC input.
2
sampled HIGH or CE
2
2
to enable the chip. CE
to enable the CY7C1354A/GVT71256ZC36. CE or
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Description
2
sampled LOW, along with ADV/LD
2
2
has inverted polarity but oth-
.
2
is used with CE
2
are used