CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet - Page 6

• Manufacturer Part Number: CY7C1354A-166BGC
• Description: IC SRAM 9MBIT 166MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1108

Pin Descriptions—256Kx36
Pin Descriptions—512Kx18
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
1, 2, 3, 6-9, 12,
51, 52, 53, 56-
14, 15, 16, 41,
40, 55, 60, 67,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 80,
81, 82, 83, 99,
68, 69, 72-75,
18, 19, 22-25,
TQFP Pins
TQFP Pins
59, 62, 63
78, 79, 80
28, 29, 30
65, 66, 91
71, 76, 90
61, 70, 77
256Kx36
512Kx18
100
37,
36,
93,
94,
64
13
38
39
43
42
84
3K, 5K, 3M, 5M,
2L, 2M, 1N, 2N,
3C, 5C, 6C, 4G,
6N, 6M, 6L, 7L,
(b) 7H, 6H, 7G,
2E, 2F, 1G, 2G,
3D, 5D, 3E, 5E,
1J, 7J, 1M, 7M,
4A, 1B, 7B, 1C,
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C,
6G, 6F, 6E, 7E,
4L, 1R, 7R, 1T,
3F, 5F, 3H, 5H,
2R, 6R, 2T, 3T,
(c) 2D, 1D, 1E,
(d) 1K, 2K, 1L,
3N, 5N, 3P, 5P
1A, 7A, 1F, 7F,
7C, 4D, 3J, 5J,
(a) 6P, 7P, 7N,
4C, 2J, 4J, 6J,
PBGA Pins
PBGA Pins
2T, 6T, 6U
256Kx36
512Kx18
1H, 2H,
6K, 7K,
7D, 6D,
4R, 5R
1U, 7U
1P, 2P
5T, 6T
2U
3U
4U
5U
4N
3G
7T
4P
5L
(continued)
Name
Name
PRELIMINARY
V
BWa,
TMS
TDO
SA0,
SA1,
BWb
DQa
DQb
DQc
DQd
TCK
V
V
TDI
NC
SA
ZZ
CCQ
CC
SS
Asynchronous
Synchronous
Synchronous
I/O Supply
Ground
Output
Output
Supply
Input-
Input-
Input-
Input/
Type
Type
Input
-
6
Snooze Enable: This active HIGH input puts the device in low
power consumption standby mode. For normal operation, this
input has to be either LOW or NC.
Data Inputs/Outputs: Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
Byte “a” is DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins;
Byte “d” is DQd pins.
IEEE 1149.1 test inputs. LVTTL-level inputs. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No
Connect) or be connected to V
IEEE 1149.1 test output. LVTTL-level output. If Serial Bound-
ary Scan (JTAG) is not used, these pins can be floating (i.e.,
No Connect).
Power Supply: +3.3V –5% and +5%.
Ground: GND.
Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V
I/O. +2.5V –0.125V and +0.4V for 2.5V I/O.
No Connect: These signals are not internally connected. It can
be left floating or be connected to V
Synchronous Address Inputs: The address register is trig-
gered by a combination of the rising edge of CLK, ADV/LD
LOW, CKE LOW, and true chip enables. SA0 and SA1 are the
two least significant bits of the address field and set the internal
burst counter if burst cycle is initiated.
Synchronous Byte Write Enables: Each 9-bit byte has its own
active LOW byte write enable. On load write cycles (when R/W
and ADV/LD are sampled LOW), the appropriate byte write
signal (BWx) must be valid. The byte write signal must also be
valid on each cycle of a burst write. Byte write signals are
ignored when R/W is sampled HIGH. The appropriate byte(s)
of data are written into the device two cycles later. BWa con-
trols DQa pins; BWb controls DQb pins. BWx can all be tied
LOW if always doing write to the entire 18-bit word.
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Description
Description
CC
.
CC
or to GND.