CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet - Page 23

• Manufacturer Part Number: CY7C1354A-166BGC
• Description: IC SRAM 9MBIT 166MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1108

Switching Waveforms
Write Timing
Notes:
44. D(A
45. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW when ADV/LD
BWa#, BWb#
in the burst sequence of the base address A
state of the MODE input.
is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM.
ADDRESS
ADV/LD#
1
) represents the first input to the external address A1. D(A
CKE#
R/W#
CLK
CE#
OE#
DQ
[40, 41, 42, 43, 44, 45]
BW(A
A
1
1
)
t
t
t
t
t
t
S
S
S
S
S
S
Pipeline Write
(continued)
BW(A
A
2
2
)
t
SD
2
PRELIMINARY
, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the
t
t
t
t
t
t
H
H
H
H
H
H
Pipeline Write
BW(A
D(A
2
1
+1)
)
t
HD
t
KC
2
) represents the first input to the external address A
t
KL
BW(A
D(A
2
+2)
2
)
23
BW(A
D(A
2
2
+3)
+1)
t
KH
(CKE# HIGH, eliminates
current L-H clock edge)
Burst Pipeline Write
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
BW(A
2
D(A
; D(A
2
+2)
2
)
2
+1) represents the next input data
D(A
2
(Burst Wraps around
+3)
to initial state)
D(A
2
)