CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet - Page 9

• Manufacturer Part Number: CY7C1354A-166BGC
• Description: IC SRAM 9MBIT 166MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1108

Functional Timing Diagram
Truth Table
Notes:
10. CE equals H means CE and CE
11. BWa enables WRITE to byte “a” (DQa pins). BWb enables WRITE to byte “b” (DQb pins). BWc enables WRITE to byte “c” (DQc pins). BWd enables WRITE to
12. The device is not in Snooze Mode, i.e. the ZZ pin is LOW.
13. During Snooze Mode, the ZZ pin is HIGH and all the address pins and control pins are “Don’t Care.” The SNOOZE MODE can only be entered two cycles after
14. All inputs, except OE, ZZ, and MODE pins, must meet set-up time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge.
15. OE may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle.
16. Device outputs are ensured to be in High-Z during device power-up.
17. This device contains a 2-bit burst counter. The address counter is incremented for all Continue Burst cycles. Address wraps to the initial address every fourth
18. Continue Burst cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ or WRITE, depends upon the R/W control
19. Dummy Read and Abort Write cycles can be entered to set up subsequent READ or WRITE cycles or to increment the burst counter.
20. When an Ignore Clock Edge cycle enters, the output data (Q) will remain the same if the previous cycle is READ cycle or remain High-Z if the previous cycle is
Deselect Cycle
Continue Deselect/NOP
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
Abort Write (Begin Burst)
Abort Write (Continue Burst)
Ignore Clock Edge/NOP
6.
7.
8.
9.
(SA0, SA1, SA )
(R/W#, BWx#,
CONTROL
ADDRESS
ADV/LD#)
This assumes that CKE, CE, CE
All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data
delay from the rising edge of clock.
DQc and DQd apply to 256Kx36 device only.
L means logic LOW. H means logic HIGH. X means “Don’t Care.” High-Z means High Impedance. BWx = L means [BWa*BWb*BWc*BWd] equals LOW. BWx
= H means [BWa*BWb*BWc*BWd] equals HIGH. BWc and BWd apply to 256Kx36 device only.
and CE
byte “d” (DQd pins). DQc, DQd, BWc, and BWd apply to 256Kx36 device only.
the WRITE cycle, otherwise the WRITE cycle may not be completed.
burst cycle.
signal at the Begin Burst cycle. A Continue Deselect cycle can only be entered if a DESELECT cycle is executed first.
WRITE or DESELECT cycle.
DQ[a:d]
DATA
CLOCK
CYCLE
2
are “Don’t Care.”
OPERATION
[9, 10, 11, 12, 13, 14, 15, 16, 17]
DQ
n+19
A
C
19
19
17
[18]
[20]
[19]
[19]
2
[18, 19]
[18]
2
[18]
are LOW along with CE
and CE
[18, 19]
n+20
DQ
A
C
[6, 7, 8]
20
20
2
18
are all True.
Previous
Deselect
PRELIMINARY
Cycle
Read
Read
Write
Write
X
X
X
X
X
X
DQ
n+21
C
A
21
21
2
19
being HIGH. CE equals L means CE or CE
Address
External
External
External
External
Used
Next
Next
Next
Next
X
X
X
DQ
n+22
A
C
22
22
20
9
R/W
H
X
X
H
X
X
X
X
X
L
L
DQ
n+23
C
A
ADV/LD
23
23
21
H
H
H
H
H
H
L
L
L
L
L
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
DQ
n+24
CE
A
C
H
X
L
X
L
X
L
X
L
X
X
2
24
24
is HIGH or CE
22
CKE
H
L
L
L
L
L
L
L
L
L
L
DQ
n+25
C
A
2
25
25
23
BWx
is LOW. CE equals X means CE, CE
X
X
X
X
X
X
H
H
X
L
L
DQ
n+26
OE
A
C
X
X
X
X
H
H
X
X
X
X
X
26
26
24
(2 cycles later)
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
n+27
DQ
Q
Q
D
D
C
A
-
27
27
25
2
,