CY7C1354A-166BGC Cypress Semiconductor Corp, CY7C1354A-166BGC Datasheet - Page 7

• Manufacturer Part Number: CY7C1354A-166BGC
• Description: IC SRAM 9MBIT 166MHZ 119BGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1354A-166BGC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1108

Pin Descriptions—512Kx18
68, 69, 72, 73, 74
8, 9, 12, 13, 18,
58, 59, 62, 63,
14, 15, 16, 41,
19, 22, 23, 24
TQFP Pins
65, 66, 91
512Kx18
98,
87
88
89
92
97
86
85
31
64
38
39
43
42
7G, 6H, 7K, 6L,
1H, 2K, 1L, 2M,
(b) 1D, 2E, 2G,
(a) 6D, 7E, 6F,
4C, 2J, 4J, 6J,
PBGA Pins
512Kx18
4R, 5R
4E, 6B
6N, 7P
1N, 2P
4M
4H
4K
2B
4B
3R
2U
3U
4U
5U
4F
7T
(continued)
ADV/LD
MODE
Name
PRELIMINARY
CKE
DQa
DQb
TMS
TDO
R/W
CLK
TCK
CE
CE
V
CE,
TDI
OE
ZZ
CC
2
2
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Output
Output
Supply
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Input-
Input/
Type
Input
Input
7
Synchronous Clock Enable Input: When CKE is sampled
HIGH, all other synchronous inputs, including clock are ig-
nored and outputs remain unchanged. The effect of CKE sam-
pled HIGH on the device outputs is as if the LOW-to-HIGH
clock transition did not occur. For normal operation, CKE must
be sampled LOW at rising edge of clock.
Read Write: R/W signal is a synchronous input that identifies
whether the current loaded cycle and the subsequent burst
cycles initiated by ADV/LD is a Read or Write operation. The
data bus activity for the current cycle takes place two clock
cycles later.
Clock: This is the clock input to CY7C1356A/GVT71512ZC18.
Except for OE, ZZ, and MODE, all timing references for the
device are made with respect to the rising edge of CLK.
Synchronous Active LOW Chip Enable: CE and CE
with CE
CE
LOW at the rising edge of clock, initiates a deselect cycle. The
data bus will be High-Z two clock cycles after chip deselect is
initiated.
Synchronous Active HIGH Chip enable: CE
and CE
erwise is identical to CE and CE
Asynchronous Output Enable: OE must be LOW to read data.
When OE is HIGH, the I/O pins are in high-impedance state.
OE does not need to be actively controlled for read and write
cycles. In normal operation, OE can be tied LOW.
Advance/Load: ADV/LD is a synchronous input that is used to
load the internal registers with new address and control signals
when it is sampled LOW at the rising edge of clock with the
chip is selected. When ADV/LD is sampled HIGH, then the
internal burst counter is advanced for any burst that was in
progress. The external addresses and R/W are ignored when
ADV/LD is sampled HIGH.
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst
sequence is selected. MODE is a static DC input.
Snooze Enable: This active HIGH input puts the device in low
power consumption standby mode. For normal operation, this
input has to be either LOW or NC.
Data Inputs/Outputs: Both the data input path and data output
path are registered and triggered by the rising edge of CLK.
Byte “a” is DQa pins; Byte “b” is DQb pins.
IEEE 1149.1 test inputs. LVTTL-level inputs. If Serial Boundary
Scan (JTAG) is not used, these pins can be floating (i.e., No
Connect) or be connected to V
IEEE 1149.1 test output. LVTTL-level output. If Serial Bound-
ary Scan (JTAG) is not used, these pins can be floating (i.e.,
No Connect).
Power Supply: +3.3V –5% and +5%.
2
sampled HIGH or CE
2
2
to enable the chip. CE
to enable the CY7C1356A/GVT71512ZC18. CE or
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Description
2
sampled LOW, along with ADV/LD
CC
2
2
has inverted polarity but oth-
.
.
2
is used with CE
2
are used