NAND512W3A2BN6F STMicroelectronics, NAND512W3A2BN6F Datasheet - Page 16

• Manufacturer Part Number: NAND512W3A2BN6F
• Description: IC FLASH 512MBIT 48TSOP
• Manufacturer: STMicroelectronics

Specifications of NAND512W3A2BN6F

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 512M (64M x 8)
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -

NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SIGNAL DESCRIPTIONS
See
3., Signal
nals connected to this device.
Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7
are used to input the selected address, output the
data during a Read operation or input a command
or data during a Write operation. The inputs are
latched on the rising edge of Write Enable. I/O0-I/
O7 are left floating when the device is deselected
or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to
15 are only available in x16 devices. They are
used to output the data during a Read operation or
input data during a Write operation. Command and
Address Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write
Enable. I/O8-I/O15 are left floating when the de-
vice is deselected or the outputs are disabled.
Address Latch Enable (AL). The Address Latch
Enable activates the latching of the Address inputs
in the Command Interface. When AL is high, the
inputs are latched on the rising edge of Write En-
able.
Command Latch Enable (CL). The
Latch Enable activates the latching of the Com-
mand inputs in the Command Interface. When CL
is high, the inputs are latched on the rising edge of
Write Enable.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
low, V
goes high, v
remains selected and does not go into standby
mode.
When the device is executing a Sequential Row
Read operation, Chip Enable must be held low
(from the second page read onwards) during the
time that the device is busy (t
able goes high during t
aborted.
Read Enable (R). The Read Enable, R, controls
the sequential data output during Read opera-
tions. Data is valid t
The falling edge of R also increments the internal
column address counter by one.
16/56
Figure
IL
, the device is selected. If Chip Enable
Names, for a brief overview of the sig-
IH
, while the device is busy, the device
2., Logic
RLQV
after the falling edge of R.
BLBH1
Diagram,
BLBH1
the operation is
). If Chip En-
and
Command
Table
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of Write En-
able.
During power-up and power-down a recovery time
of 1µs (min) is required before the Command Inter-
face is ready to accept a command. It is recom-
mended to keep Write Enable high during the
recovery time.
Write Protect (WP). The Write Protect pin is an
input that gives a hardware protection against un-
wanted program or erase operations. When Write
Protect is Low, V
program or erase operations.
It is recommended to keep the Write Protect pin
Low, V
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the P/E/R Controller is currently active.
When Ready/Busy is Low, V
erase operation is in progress. When the operation
completes Ready/Busy goes High, V
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Refer to the
teristics
value of the pull-up resistor.
V
supply to the internal core of the memory device.
It is the main power supply for all operations (read,
program and erase).
An internal voltage detector disables all functions
whenever V
1.5V (for 1.8V devices) to protect the device from
any involuntary program/erase during power-tran-
sitions.
Each device in a system should have V
pled with a 0.1µF capacitor. The PCB track widths
should be sufficient to carry the required program
and erase currents
V
the power supply. It must be connected to the sys-
tem ground.
DD
SS
Ground. Ground, V
Supply Voltage. V
IL
section for details on how to calculate the
, during power-up and power-down.
DD
Ready/Busy Signal Electrical Charac-
is below 2.5V (for 3V devices) or
IL
, the device does not accept any
DD
SS,
OL
provides the power
is the reference for
, a read, program or
OH
.
DD
decou-