TC58FVM6T5BTG65 Toshiba, TC58FVM6T5BTG65 Datasheet - Page 13

• Manufacturer Part Number: TC58FVM6T5BTG65
• Description: IC FLASH 64MBIT 65NS 48TSOP
• Manufacturer: Toshiba

Specifications of TC58FVM6T5BTG65

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 65ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

10.14. Program Suspend/Resume Mode
command in Write Mode (including Write operations performed during Erase Suspend) but ignores the command in other
modes. When the command is input, the address of the bank on which Write is being performed must be specified. In Program
Suspend Mode, it is invalid except a Read command, a ID Read command, a CFI command, and a Resume command. After
input of the command, the device will enter Program Suspend Read Mode after t
the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual.
command, specify the address of the bank on which Write is being performed. If the ID Read or CFI Data Read function is
being used, abort the function before inputting the Resume command. On receiving the Resume command, the device returns
to Write Mode and resumes outputting the Hardware Sequence flag for the bank to which data is being written.
Suspend in Acceleration Mode, V
10.15. Auto Chip Erase Mode
command in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the
chip. The device status is indicated by the Hardware Sequence flag.
Auto Chip Erase operation is interrupted, it cannot be completed correctly. Hence, an additional Erase operation must be
performed.
and the device will enter Read mode 400 μs after the latch of command in the sixth bus cycle.
device status is indicated by the Hardware Sequence flag. Either a Reset command or a hardware reset is required to return
the device to Read Mode after a failure.
perform a Block Erase on each block, identify the failed blocks, and stop using them. To build a more reliable system, the host
processor should take measures to prevent subsequent use of failed blocks
10.16. Auto Block Erase/Auto Multi-Block Erase Modes
latched in the sixth bus cycle. The auto block erase starts as soon as the Erase Hold Time (t
the command. When multiple blocks are erased, the sixth Bus Write cycle is repeated with each block address and Auto Block
Erase command being input within the Erase Hold Time (this constitutes an Auto Multi-Block Erase operation). If a command
other than an Auto Block Erase command or Erase Suspend command is input during the Erase Hold Time, the device will
reset the Command Register and enter Read Mode. The Erase Hold Time restarts on each successive command latch. Once
operation starts, all memory cells in the selected block are automatically preprogrammed to 0, erased and verified as erased by
the chip. The device status is indicated by the setting of the Hardware Sequence flag. When the Hardware Sequence flag is
read, the addresses of the blocks on which auto-erase operation is being performed must be specified. If the selected blocks are
spread across all 8 banks, simultaneous operation cannot be carried out.
operation can be aborted using a Hardware Reset. If an auto-erase operation is interrupted, it cannot be completed correctly;
therefore, a further erase operation is necessary to complete the erasing.
executed and the device returns to Read Mode 400 μs after the latch of command in the last bus cycle.
is indicated by the Hardware Sequence flag. After a failure, either a Reset command or a Hardware Reset is required to return
the device to Read Mode. If multiple blocks are selected, it will not be possible to ascertain the block in which the failure
occurred. In this case either abandon use of the device altogether, or perform a Block Erase on each block, identify the failed
blocks, and stop using them. To build a more reliable system, the host processor should take measures to prevent subsequent
use of failed blocks.
Program Suspend is used to enable Data Read by suspending the Write operation. The device accepts a Program Suspend
During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is suspended,
After completion of Program Suspend, input a Program Resume command to return to Write Mode. When inputting the
Program Suspend can be run in Fast Program Mode or Acceleration Mode. However, note that when running Program
The Auto Chip Erase Mode is set using the Chip Erase command. An Auto Chip Erase operation starts on the latch of the
Command input is ignored during an Auto Chip Erase. A hardware reset can interrupt an Auto Chip Erase operation. If an
Any attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed
If an Auto Chip Erase operation fails, the device will remain in the erasing state and will not return to the Read Mode. The
In this case, it cannot be ascertained which block the failure occurred in. Either abandon use of the device altogether, or
The Auto Block Erase Mode and Auto Multi-Block Erase Mode are set using the Block Erase command. The block address is
All commands (except Erase Suspend) are ignored during an Auto Block Erase or Auto Multi-Block Erase operation. Either
Any attempt to erase a protected block is ignored. If all the selected blocks are protected, the auto-erase operation is not
If an auto-erase operation fails, the device remains in the Erasing state and does not return to Read Mode. The device status
ACC
must not be released.
TC58FVM6(T/B)5B(TG/XG)65
SUSP
.
BEH
) has elapsed after the latch of
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