ISL9216IRZ Intersil, ISL9216IRZ Datasheet - Page 14

• Manufacturer Part Number: ISL9216IRZ
• Description: IC MULTI-CELL LI-ION PROT 32-QFN
• Manufacturer: Intersil

Specifications of ISL9216IRZ

• Function: Battery Monitor
• Battery Type: Lithium-Ion (Li-Ion)
• Voltage - Supply: 9.2 V ~ 31 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Registers
NOTES:
10. This SLEEP bit is cleared on initial power-up, by the WKUP pin going high (when WKPOL = ”1”) or by the WKUP pin going low (when
12. The shaded registers are not used in the ISL9217 device. Shaded status registers return ‘0’ when read. Shaded “read/write” registers can be read
11. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns
ADDR
7. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
8. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, 6, 7, and 8: write a reserved bit
9. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.
09H:
FFH
00H
01H
02H
03H
04H
05H
06H
07H
08H
with the value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.
WKPOL = ”0”), and by writing a “0” to the location with an I
off the FETs. At all other times, an I
drive output circuit (though not the actual voltage at the output pin).
and written, but they provide no functionality. When writing to the shaded areas in the ISL9217, the locations must be written as “0”.
Operating Status
Discharge Set
Configuration
Cell Balance
Write Enable
FET Control
Feature Set
REGISTER
Charge Set
Analog Out
Reserved
(Note 9)
Status
READ/WRITE
DISSETEN bit
CHSETEN bit
(Write only if
(Write only if
(Write only if
FSETEN bit
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read only
Read only
14
set)
set)
set)
NA
2
C write operation controls the output to the respective FET and a read returns the current state of the FET
User Flag 1
Cascade U
ATMPOFF
temp scan
Reserved
DENOCD
automatic
DENOCC
automatic
automatic
Set writes
(Note 10)
FSETEN
CB7ON
external
Turn off
Turn off
Turn off
Feature
UFLG1
SLEEP
Enable
control
control
Force
Sleep
OCD
OCC
CU
7
Cell balance FET control bits (plus WKUP of ISL9217 in cascade)
Disable 3.3V
User Flag 0
reg. (device
LDMONEN
Charge Set
connection
Cascade L
CHSETEN
Reserved
Configure Overcurrent
Configure Overcurrent
CB6ON/
WKUPR
requires
Discharge Threshold
external
Turn on
OCDV1
OCCV1
UFLG0
ISL9216, ISL9217
Enable
VMON
writes
Charge Threshold
3.3V)
DIS3
CL
TABLE 1. REGISTERS
6
2
C command.
DISSETEN
Temp 3.3V
Reserved
Reserved
Reserved
Discharge
Set writes
TMP3ON
Ext over
keep on
CB5ON
OCDV0
OCCV0
Enable
temp
XOT
5
SCD control
circuit delay
Long Short-
User Flag 3
WKUP pin
Reserved
Reserved
automatic
SCLONG
DISXTSD
shutdown
DENSCD
CB4ON
external
Turn off
Int over
Disable
thermal
UFLG3
WKUP
Status
Temp
IOT
4
RESERVED
User Flag 2
time by 32
Reserved
Reserved
Configure Short Circuit
shutdown
Load Fail
DISITSD
(VMON)
Discharge Threshold
LDFAIL
CB3ON
SCDV1
Disable
internal
thermal
UFLG2
CTDIV
charge
Divide
AO3
3
Analog output select bits
Force POR
time by 64
Reserved
Reserved
Reserved
discharge
CB2ON
SCDV0
DTDIV
Circuit
Divide
Short
DSC
POR
AO2
2
DISWKUP
WKUP pin
Reserved
Discharge
Reserved
Configure Overcurrent
Configure Overcurrent
(Note 11)
CB1ON
Turn on
Charge
OCDT1
OCCT1
Disable
Discharge Time-out
CFET
DOC
AO1
FET
Charge Time-out
OC
1
November 2, 2007
Charge OC
Reserved
Reserved
Reserved
Disharge
(Note 11)
Wake-up
Turn on
WKPOL
OCDT0
OCCT0
Polarity
DFET
COC
FN6488.1
AO0
FET
0