HIP6602BCBZ Intersil, HIP6602BCBZ Datasheet - Page 7

• Manufacturer Part Number: HIP6602BCBZ
• Description: IC DRIVER MOSFET QUAD 14-SOIC
• Manufacturer: Intersil

Specifications of HIP6602BCBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Current - Peak: 400mA
• Number Of Configurations: 2
• Number Of Outputs: 4
• High Side Voltage - Max (bootstrap): 15V
• Voltage - Supply: 10.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -

A falling transition on PWM indicates the turn-off of the
upper MOSFET and the turn-on of the lower MOSFET. A
short propagation delay [TPDL
before the upper gate begins to fall [TF
adaptive shoot-through circuitry determines the lower gate
delay time, TPDH
and the lower gate is allowed to rise after PHASE drops
below 0.5V. The lower gate then rises [TR
on the lower MOSFET.
Three-State PWM Input
A unique feature of the HIP6602B drivers is the addition of a
shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the Electrical Specifications determine
when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
The drivers incorporate adaptive shoot-through protection to
prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 2.2V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 0.5V, the LGATE
is allowed to rise. If the PHASE does not drop below 0.5V
within 250ns, LGATE is allowed to rise. This is done to
generate the bootstrap refresh signal. PHASE continues to
be monitored during the lower gate rise time. If the PHASE
voltage exceeds the 0.5V threshold during this period and
remains high for longer than 2µs, the LGATE transitions low.
This is done to make the lower MOSFET emulate a diode.
Both upper and lower gates are then held low until the next
rising edge of the PWM signal.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.95V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of
7.6V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.
Internal Bootstrap Device
The HIP6602B features an internal bootstrap device. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
LGATE
. The PHASE voltage is monitored
7
UGATE
] is encountered
UGATE
LGATE
]. Again, the
], turning
HIP6602B
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V. The bootstrap capacitor can be
chosen from the following equation:
Where Q
charge the gate of the upper MOSFET. The ∆V
defined as the allowable droop in the rail of the upper drive.
As an example, suppose a HUF76139 is chosen as the
upper MOSFET. The gate charge, Q
sheet is 65nC for a 10V upper gate drive. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.325µF is required.
The next larger standard value capacitance is 0.33µF.
In applications which require down conversion from +12V or
higher and PVCC is connected to a +12V source, a boot
resistor in series with the boot capacitor is required. The
increased power density of these designs tend to lead to
increased ringing on the BOOT and PHASE nodes, due to
faster switching of larger currents across given circuit
parasitic elements. The addition of the boot resistor allows
for tuning of the circuit until the peak ringing on BOOT is
below 29V from BOOT to GND and 17V from BOOT to VCC.
A boot resistor value of 5Ω typically meets this criteria.
In some applications, a well tuned boot resistor reduces the
ringing on the BOOT pin, but the PHASE to GND peak
ringing exceeds 17V. A gate resistor placed in the UGATE
trace between the controller and upper MOSFET gate is
recommended to reduce the ringing on the PHASE node by
slowing down the upper MOSFET turn-on. A gate resistor
value between 2Ω to 10Ω typically reduces the PHASE to
GND peak ringing below 17V.
Gate Drive Voltage Versatility
The HIP6602B provides the user flexibility in choosing the
gate drive voltage. Simply applying a voltage from 5V up to
12V on PVCC will set both driver rail voltages.
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency and total gate charge of the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 14 lead SOIC package is approximately
1000mW. Improvements in thermal transfer may be gained by
increasing the PC board copper area around the HIP6602B.
Adding a ground pad under the IC to help transfer heat to the
outer peripheral of the board will help. Also keeping the leads to
the IC as wide as possible and widening this these leads as
soon as possible to further enhance heat transfer will also help.
When designing the driver into an application, it is
recommended that the following calculation be performed to
C
BOOT
≥
GATE
----------------------- -
∆V
Q
GATE
BOOT
is the amount of gate charge required to fully
GATE
, from the data
BOOT
July 22, 2005
term is
FN9076.5