HIP6602BCBZ Intersil, HIP6602BCBZ Datasheet - Page 8

• Manufacturer Part Number: HIP6602BCBZ
• Description: IC DRIVER MOSFET QUAD 14-SOIC
• Manufacturer: Intersil

Specifications of HIP6602BCBZ

• Configuration: High and Low Side, Synchronous
• Input Type: PWM
• Current - Peak: 400mA
• Number Of Configurations: 2
• Number Of Outputs: 4
• High Side Voltage - Max (bootstrap): 15V
• Voltage - Supply: 10.8 V ~ 13.2 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -

ensure safe operation at the desired frequency for the
selected MOSFETs. The total chip power dissipation is
approximated as:
P = 1.05 x f
where f
and Q
MOSFET selection and any external capacitance added to
the gate pins. The I
of the driver and is typically 40mW.
The 1.05 term is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. C
capacitors. Decoupling capacitors [0.15µF] are added to the
PVCC and VCC pins. The bootstrap capacitor value in the
test circuit is 0.01µF.
The power dissipation approximation is a result of power
transferred to and from the upper and lower gates. But, the
internal bootstrap device also dissipates power on-chip
during the refresh cycle. Expressing this power in terms of
the upper MOSFET total gate charge is explained below.
The bootstrap device conducts when the lower MOSFET or
its body diode conducts and pulls the PHASE node toward
GND. While the bootstrap device conducts, a current path is
formed that refreshes the bootstrap capacitor. Since the
upper gate is driving a MOSFET, the charge removed from
the bootstrap capacitor is equivalent to the total gate charge
of the MOSFET. Therefore, the refresh power required by
the bootstrap capacitor is equivalent to the power used to
charge the gate capacitance of the upper MOSFETs.
where Q
capacitors and provided to the upper gate loads.
P
REFRESH
L
sw
is the upper and lower gate charge determined by
LOSS
SW
is the switching frequency of the PWM signal. Q
U
=
x V
and C
f
is the total charge removed from the bootstrap
SW
PVCC
Q
DDQ
LOSS
L
[
are the upper and lower gate load
3
_
2
(Q
VCC product is the quiescent power
V
U1
PVCC
+ Q
8
U2
=
) + (Q
f
SW
Q
L1
U
+ Q
V
PVCC
L2
)
]
+ I
DDQ
x VCC
HIP6602B
U
In Figure 2, C
is varied from 10kHz to 1.5MHz. PVCC and VCC are tied
together to a +12V supply.
Figure 3 shows the dissipation in the driver with 1nF loading
on both gates and each individually. Figure 4 is the same as
Figure 3 except the capacitance is increased to 3nF.
The impact of loading on power dissipation is shown in
Figure 5. Frequency is held constant while the gate
capacitors are varied from 1nF to 5nF. VCC and PVCC are
tied together and to a +12V supply. Figures 6, 7 and 8 show
the same characterization for PVCC tied to +5V instead of
+12V. The gate supply voltage, PVCC, within the HIP6602B
sets both upper and lower gate driver supplies at the same
5V level for the last three curves.
Test Circuit
+12V
+5V OR +12V
0.15µF
FIGURE 1. HIP6602B TEST CIRCUIT
0.15µF
PWM1
PWM2
U
PGND
PVCC
+5V OR +12V
GND
VCC
and C
L
values are the same and frequency
BOOT1
0.01µF
UGATE2
PHASE2
UGATE1
PHASE1
BOOT2
LGATE2
LGATE1
0.01µF
C
C
2N7002
2N7002
L
L
2N7002
2N7002
100kΩ
100kΩ
July 22, 2005
C
C
U
U
FN9076.5