ISL6269CRZ Intersil, ISL6269CRZ Datasheet - Page 9

• Manufacturer Part Number: ISL6269CRZ
• Description: IC CTRLR PWM 1-PHASE GPU 16-QFN
• Manufacturer: Intersil

Specifications of ISL6269CRZ

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 600kHz
• Voltage - Supply: 7 V ~ 25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Frequency-max: 600kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -

improved with a reduction of unnecessary switching losses
by reducing the PWM frequency. It is characteristic of the R
architecture for the PWM frequency to decrease while in
diode emulation. The extent of the frequency reduction is
proportional to the reduction of load current. The ISL6269
features an audio filter that clamps the minimum PWM
frequency to a level beyond human hearing when the output
load current becomes low enough.
With FCCM pulled low, the converter will automatically enter
DEM after the PHASE pin has detected positive voltage,
while the LG gate-driver pin is high, for eight consecutive
PWM pulses. The converter will return to CCM on the
following cycle after the PHASE pin detects negative
voltage, indicating that the body diode of the low-side
MOSFET is conducting positive inductor current.
Overcurrent and Short-Circuit Protection
The overcurrent protection (OCP) and short circuit protection
(SCP) setpoint is programmed with resistor R
connected across the ISEN and PHASE pins. The PHASE pin
is connected to the drain terminal of the low-side MOSFET.
The SCP setpoint is internally set to twice the OCP setpoint.
When an OCP or SCP fault is detected, the PGOOD pin will
pulldown to
remain latched until the EN pin has been pulled below the
falling EN threshold voltage V
below the falling POR threshold voltage
The OCP circuit does not directly detect the DC load current
leaving the converter. The OCP circuit detects the peak of
positive-flowing output inductor current. The low-side
MOSFET drain current I
positive output inductor current when the high-side MOSFET
is off. The inductor current develops a negative voltage
across the r
measured shortly after the LG gate-driver output goes high.
The ISEN pin sources the OCP sense current I
the OCP programming resistor R
zero volts with respect to the GND pin. The negative voltage
across the PHASE and GND pins is nulled by the voltage
dropped across R
fault occurs if I
I
PHASE and GND pins. I
PWM pulses that occur within 20µs. If I
on a PWM pulse before 20µs has elapsed, the timer will be
reset. An SCP fault will occur within 10µs when I
exceeds twice I
written as:
The value of R
I
R
OC
SEN
SEN
while attempting to null the negative voltage across the
•
R
=
SEN
⎛
⎝
----------------------------------------------------------------------------
I
FL
DS(ON)
30Ω
=
+
SEN
I
SEN
I
-------- -
D
OC.
PP
2
and latch off the converter. The fault will
•
r
SEN
⎞ OC
⎠
DS ON
•
rises above the OCP threshold current
is then written as:
of the low-side MOSFET that is
The relationship between I
I
OC
(
as I
SP
D
SEN
)
•
is assumed to be equal to the
SEN
r
DS ON
must exceed I
ENTHF
9
(
conducts through it. An OCP
SEN,
)
or if V
forcing the ISEN pin to
SEN
V
VCC_THF
VCC
OC
falls below I
SEN
D
SEN,
on all the
has decayed
and I
SEN
that is
.
through
SEN
(EQ. 3)
(EQ. 4)
OC
is
3
ISL6269
Where:
Overvoltage Protection
When an OVP fault is detected, the PGOOD pin will
pull-down to 60Ω and latch-off the converter. The OVP fault
will remain latched until the V
falling POR threshold voltage
The OVP fault detection circuit triggers after the voltage
across the FB and GND pins has increased above the rising
overvoltage threshold V
latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET
on and off, in response to the output voltage transversing the
V
Undervoltage Protection
When a UVP fault is detected, the PGOOD pin will pull down
to 95Ω and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V
falling POR threshold voltage
detection circuit triggers after the voltage across the FB and
GND pins has fallen below the undervoltage threshold V
Over-Temperature
When the temperature of the ISL6269 increases above the
rising threshold temperature T
state that suspends the PWM , forcing the LG and UG
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V
V
V
during OTP. It is likely that the IC will detect an UVP fault
because in the absence of PWM, the output voltage
immediately decays below the undervoltage threshold V
the PGOOD pin will pull-down to 95Ω and latch-off the
converter. The UVP fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
V
threshold voltage
VCC_THF
OVR
VCC
ENTHF
- R
- I
- I
- I
- I
- OC
overcurrent setpoint
the ISEN pin
pin that will activate the OCP circuit
a multiplier relative to I
SEN
OC
FL
PP
SEN
decays below the falling POR threshold voltage
and V
SP
is the maximum continuous DC load current
is the inductor peak-to-peak ripple current
is the I
or if V
is the current sense current that is sourced from
. All other protection circuits function normally
(Ω) is the resistor used to program the
is the desired overcurrent setpoint expressed as
OVF
VCC
SEN
thresholds.
V
ENTHF
VCC_THF
has decayed below the falling POR
threshold current sourced from the ISEN
OVR.
OTHYS
or if V
FL
.
VCC
Although the converter has
V
V
OTR
VCC_THF
VCC_THF
VCC
at which time normal PWM
has decayed below the
, the IC will enter an OTP
has decayed below the
.
. The UVP fault
ENTHF
June 25, 2009
FN9177.3
UV
or if
UV
;
.