ISL6316IRZ-T Intersil, ISL6316IRZ-T Datasheet - Page 17

• Manufacturer Part Number: ISL6316IRZ-T
• Description: IC CTRLR PWM 4PHASE ENH 40-QFN
• Manufacturer: Intersil

Specifications of ISL6316IRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

voltage under load can effectively be level shifted down so
that a larger positive spike can be sustained without crossing
the upper specification limit.
As shown in Figure 8, a current proportional to the average
current of all active channels, I
load-line regulation resistor R
across R
creating an output voltage droop with a steady-state value
defined as:
The regulated output voltage is reduced by the droop voltage
V
derived by combining Equation 8 with the appropriate sample
current expression defined by the current sense method
employed.
Where V
programmed offset voltage, I
the converter, R
ISEN+ pin, and R
channel number, and R
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to:
Output-Voltage Offset Programming
The ISL6316 allows the designer to accurately adjust the
offset voltage. When a resistor, R
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I
is connected to ground, the voltage across it is regulated to
0.4V, and I
REF, R
equal to the desired offset voltage. These functions are shown
in Figure 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R
For Positive Offset (connect R
For Negative Offset (connect R
V
V
R
R
R
DROOP
DROOP
OUT
LL
OFS
OFS
=
=
=
=
REF
------------
R
. The output voltage as a function of load current is
REF
FB
N
V
1.6
----------------------------- -
0.4
----------------------------- -
FB
V
V
=
OFS
REF
, is selected so that the product (I
OFFSET
OFFSET
is proportional to the output current, effectively
I
×
×
----------------- -
R
AVG
is the reference voltage, V
R
R
ISEN
R
–
flows out of OFS. A resistor between DAC and
ISEN
REF
REF
X
V
R
FB
OFS
FB
is the feedback resistor, N is the active
is the sense resistor connected to the
–
X
⎛
⎜
⎝
I
------------ -
is the DCR, r
OUT
N
OUT
FB
17
OFS
AVG
----------------- - R
R
OFS
OFS
. The resulting voltage drop
ISEN
R
OFS
is the total output current of
X
, flows from FB through a
OFS
to VCC):
) to flow into OFS. If R
to GND):
, is connected between
DS(ON)
:
FB
OFS
⎞
⎟
⎠
OFS
is the
, or R
x R
SENSE
OFS
(EQ. 10)
(EQ. 11)
(EQ. 12)
(EQ. 8)
(EQ. 9)
) is
OFS
ISL6316
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs during regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner. Supervising
the safe output voltage transition within the DAC range of the
processor without discontinuity or disruption is a necessary
function of the core-voltage regulator.
The ISL6316 checks the VID inputs six times every switching
cycle. If the VID code is found to have been changed, the
controller waits for half of a switching cycle before executing a
6.25mV step change. If the difference between DAC level and
the new VID code changes during the half-cycle waiting
period, no change to the DAC output is made. If the VID code
is more than 1-bit higher or lower than the DAC (not
recommended), the controller will execute 6.26mV step
change six times per cycle until VID and DAC are equal.
Therefore it is important to carefully control the rate of VID
stepping in 1-bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R
R
in Output-Voltage Offset Programming. The selection of C
is based on the time duration for 1-bit VID change and the
allowable delay time.
REF
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
is based on the desired offset voltage as detailed above
1.6V
VCC
+
-
REF
and C
0.4V
E/A
GND
+
-
REF
FB
, can be used. The selection of
DYNAMIC
VID D/A
ISL6316
December 12, 2006
DAC
OFS
GND
VCC
OR
FN9227.1
REF
R
R
REF
REF
OFS