ISL6316IRZ-T Intersil, ISL6316IRZ-T Datasheet - Page 24

IC CTRLR PWM 4PHASE ENH 40-QFN

ISL6316IRZ-T

Manufacturer Part Number
ISL6316IRZ-T
Description
IC CTRLR PWM 4PHASE ENH 40-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6316IRZ-T

Pwm Type
Voltage Mode
Number Of Outputs
1
Frequency - Max
275kHz
Duty Cycle
66.7%
Voltage - Supply
4.75 V ~ 5.25 V
Buck
Yes
Boost
No
Flyback
No
Inverting
No
Doubler
No
Divider
No
Cuk
No
Isolated
No
Operating Temperature
-40°C ~ 85°C
Package / Case
40-VFQFN, 40-VFQFPN
Frequency-max
275kHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
A third component involves the lower MOSFET’s reverse-
recovery charge, Q
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q
through the upper MOSFET across VIN. The power
dissipated as a result is P
Finally, the resistive part of the upper MOSFET’s is given in
Equation 27 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 24, 25, and 26. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
different switching frequencies.
Current Sensing Resistor
The resistors connected between these pins and the
respective phase nodes determine the gains in the load-line
regulation loop and the channel-current balance loop as well
as setting the overcurrent trip point. Select values for these
resistors based on the room temperature r
MOSFETs, DCR of inductor or additional resistor; the full-load
operating current, I
Equation 28.
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistor. When the components of
one or more channels are inhibited from effectively dissipating
their heat so that the affected channels run hotter than
desired, choose new, smaller values of RISEN for the affected
phases (see the section entitled Channel-Current Balance).
Choose R
temperature rise in order to cause proportionally less current
to flow in the hotter phase.
In Equation 29, make sure that ΔT
rise above the ambient temperature, and ΔT
temperature rise above the ambient temperature. While a
single adjustment according to Equation 29 is usually
sufficient, it may occasionally be necessary to adjust R
two or more times to achieve optimal thermal balance
between all channels.
P
P
R
R
UP 3 ,
UP 4 ,
ISEN
ISEN 2 ,
=
=
r
DS ON
V
=
---------------------- -
70 10
ISEN,2
IN
R
(
R
×
Q
ISEN
X
rr
)
f
S
6
in proportion to the desired decrease in
UP,4
I
----- -
ΔT
----------
ΔT
N
M
I
------- -
FL
rr
FL
N
. Since the inductor current has fully
2
1
2
; and the number of phases, N using
.
d
+
UP,3
I
---------- - d
P-P
12
2
24
and is approximately:
2
is the desired temperature
rr
, it is conducted
DS(ON)
1
is the measured
of the lower
(EQ. 27)
(EQ. 26)
(EQ. 28)
(EQ. 29)
ISEN
ISL6316
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R
value depends on the desired full-load droop voltage
(V
ISEN resistor, the load-line regulation resistor is as shown in
Equation 30.
If one or more of the ISEN resistors is adjusted for thermal
balance, as in Equation 29, the load-line regulation resistor
should be selected according to Equation 31 where I
full-load operating current and R
connected to the n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar manner
to a peak-current mode controller because the two poles at
the output-filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final locations of these poles are determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are affected by the values of
the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
R
R
FB
FB
DROOP
=
=
V
------------------------ -
------------------------------ -
I
70 10
FL
V
DROOP
DROOP
×
r
in Figure 8). If Equation 28 is used to select each
DS ON
(
6
)
th
n
ISEN pin.
R
ISEN n ( )
C
and C
ISEN(n)
C
.
is the ISEN resistor
FB
in Figure 8. Its
December 12, 2006
FL
(EQ. 31)
(EQ. 30)
FN9227.1
is the

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