ISL6316IRZ-T Intersil, ISL6316IRZ-T Datasheet - Page 23

• Manufacturer Part Number: ISL6316IRZ-T
• Description: IC CTRLR PWM 4PHASE ENH 40-QFN
• Manufacturer: Intersil

Specifications of ISL6316IRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

close to the power stage and used to form R
non-linear temperature characteristics of the NTC, a resistor
network is needed to make the equivalent resistance between
FB and VDIFF pin is reverse proportional to the temperature.
The external temperature compensation network can only
compensate the temperature impact on the droop, while it has
no impact to the sensed current inside ISL6316. Therefore
this network cannot compensate for the temperature impact
on the overcurrent protection function.
Current Sense Output
The current from IDROOP pin is the sensed average current
inside ISL6316. In typical application, IDROOP pin is
connected to FB pin for the application where load line is
required. When load line function is not needed, IDROOP pin
can used to obtain the load current information: with one
resistor from IDROOP pin to GND, the voltage at IDROOP pin
will be proportional to the load current. The resistor from
IDROOP to GND should be chosen to ensure that the voltage
at IDROOP pin is less than 2V under the maximum load
current.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and example
board layouts for all common microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination depends
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally,
the designer will be concerned with whether components can
be mounted on both sides of the circuit board; whether through-
hole components are permitted; and the total board space
available for power-supply circuitry. Generally speaking, the
most economical solutions are those in which each phase
handles between 15 and 20A. All surface-mount designs will
tend toward the lower end of this current range. If through-hole
MOSFETs and inductors can be used, higher per-phase
currents are possible. In cases where board space is the
limiting constraint, current can be pushed as high as 40A per
phase, but these designs require heat sinks and forced air to
cool the MOSFETs, inductors and heat-dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
23
FB
. Due to the
ISL6316
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower MOSFET
is due to current conducted through the channel resistance
(r
output current; I
Equation 1); d is the duty cycle (V
channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the lower-
MOSFET body diode. This term is dependent on the diode
forward voltage at I
and the length of dead times, t
the end of the lower-MOSFET conduction interval
respectively.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P
P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times;
the lower-MOSFET body-diode reverse-recovery charge, Q
and the upper MOSFET r
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the lower
MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 24,
the required time for this commutation is t
approximated associated power loss is P
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
P
P
P
P
DS(ON)
LOW,2
LOW 1
LOW 2
UP 1 ,
UP 2 ,
,
,
≈
≈
.
V
V
). In Equation 22, I
=
=
IN
IN
r
V
⎛
⎝
⎛
⎜
⎝
DS ON
D ON
I
----- -
N
I
----- -
N
M
M
(
DS(ON)
(
+
–
IN
P-P
I
---------- -
I
---------- -
) during switching. Since a substantially
)
P-P
P-P
)
2
2
f
M
S
is the peak-to-peak inductor current (see
⎛
⎜
⎝
, V
⎞ t
⎠
⎞ t
⎟
⎠
I
----- -
N
M
⎛
⎝
losses, a large portion of the upper-
⎛
⎜
⎝
⎛
⎜
⎝
I
----- -
⎞
⎟
⎠
N
----
D(ON)
M
----
2
2
2
1
2
⎞
⎟
⎠
DS(ON)
⎞
⎟
⎠
(
+
1 d
f
f
M
S
I
---------- -
S
–
P-P
UP,2
2
is the maximum continuous
; the switching frequency, f
2
d1
. In Equation 25, the
)
⎞ t
⎠
+
and t
.
conduction loss.
d1
OUT
I
---------------------------------- -
L P-P
,
2
+
d2
/V
⎛
⎜
⎝
12
I
----- -
(
, at the beginning and
N
IN
M
1 d
UP,1
1
); and L is the per-
–
–
and the
I
---------- -
P-P
)
2
.
⎞
⎟
⎠
December 12, 2006
t
LOW,1
d2
(EQ. 22)
(EQ. 23)
(EQ. 24)
(EQ. 25)
FN9227.1
S
and
;
rr
;